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參數(shù)資料
| 型號： | NT6862 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-Bit Microcontroller for Monitor |
| 中文描述： | 8位微控制器的監(jiān)控 |
| 文件頁數(shù)： | 22/57頁 |
| 文件大?。?/td> | 580K |
| 代理商： | NT6862 |
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NT6862-5xxxx
22
12.2. Port1: P10 - P16
PORT10 - PORT16 is a 7-bit bi-directional CMOS I/O port
with PMOS as internal pull-up (Figure 12.1). Each bi-
directional I/O pin may be bit programmed as an input or
output port without software control the data direction
register. When PORT1 works as output, the data to be
output is latched to the port data register and output to the
pin. PORT1 pins that have '1's written to them are pulled
HIGH by the internal PMOS pull-ups. In this state they can
be used as input, then the input signal can be read. This
port output HIGH after reset.
P10 & P11 are shared with AD0 & AD1 input pins
respectively. If the ENADC0/1 bit in the ENADC control
register is cleared to LOW, A/D converters will activate
simultaneously. After the chip is reset, ENADC0/1 bits will
be in the HIGH state and P10 - P11 will act as I/O pins.
P12
OUTPUT pins by accessing the OUTCON control register.
If the ENHALF bit is cleared to LOW, P13 will switch to
HALFHI pin (input pin) and P12 will switch to HALFHO pin
(output pin, Figure 12.3). For HALFHI & HALFHO pin
description, please refer half frequency function in the H/V
P13 are shared with HALF SIGNALS input and
sync processor paragraph. After the chip is reset, the
ENHALF bits will be in HIGH state and P12
as I/O pins.
P13 will act
P14 is shared with output pin of self test pattern. If users
clear the PATTERN bit in the SYNCON control register
and the free running function has been activated, the P14
will switch to output pin of the self test pattern. This pattern
output pin is push-pull structure. After the chip is reset,
PATTERN bits will be in the HIGH state and P14 will act as
I/O pin. (Refer the 'Syncprocessor' section for more
detailed information.)
P15 & P16 can be shared with external interrupt INTE0 &
INTE1 pins if the INTE0/1 bits are set in the control register
of interrupt enable ($0016 & $0019). These interrupt pin
have 'Schmitt Trigger' input buffers. After the chip is reset,
INTE0/1 bits will be in HIGH state and P15 & P16 will act
as I/O pin.
Refer 'INTERRUPT CONTROLLER' paragraph above for
more details about the interrupt function.
Addr.
$0001
$000C
Register
PT1
FREECON
INIT
7FH
FFH
Bit7
-
Bit6
P16
Bit5
P15
-
Bit4
P14
-
Bit3
P13
-
Bit2
P12
FREQ2
Bit1
P11
Bit0
P10
R/W
RW
W
ENPAT
PAT0
-
FREQ1
FREQ0
$0010
ENADC
FFH
CSTA
-
-
ENADC3
ENADC2
ENADC1
ENADC0
W
$0018
$001B
IENMI
IEIRQ2
00H
00H
-
-
-
-
-
-
-
-
-
-
-
INTE0
INTE1
INTMUTE
INTMR
RW
RW
INTV
Data Input
I/P
V
DD
Figure 12.4. Schmitt Input Structure
V
DD
I/O
Data Out
.
Data OE
Data In
Figure 12.5. I/O
Structure
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