參數(shù)資料
型號(hào)： NT6862
廠商： Electronic Theatre Controls, Inc.
英文描述： 8-Bit Microcontroller for Monitor
中文描述： 8位微控制器的監(jiān)控
文件頁(yè)數(shù)： 16/57頁(yè)
文件大?。?/td> 580K
代理商： NT6862
NT6862-5xxxx
16
PWM DACs
(continued)
DAC0 & DAC1 are shared with ADC2 & ADC3 input pins respectively. If ENADC2/
3
bit in the ENADC control register is
cleared to LOW, A/D converters will activate simultaneously. After the chip is reset, ENADC2/
3
bits will be in HIGH state
and DAC0 & DAC1 will act as PWM output pins.
DAC4 & DAC5 are shared with SCL1 & SDA1 I/O pins respectively. If users clear the
ENDDC
bit in the CH1CON control
register to LOW, channel 1 of DDC will be activated. When used as DDC channel, the I/O port will be an open drain structure
and include a Schmitt Trigger buffer for noise immunity. After the chip is reset,
ENDDC
bits will be in HIGH state and DAC4
- DAC5 will act as PWM output pins.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$000F
ENDAC
FFH
-
-
ENDK12
ENDK11
ENDK10
ENDK9
ENDK8
ENDK7
W
$0010
ENADC
FFH
CSTA
-
-
-
ENADC3
ENADC2
ENADC1
ENADC0
W
$0030
DACH0
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0031
DACH1
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0032
DACH2
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0033
DACH3
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0034
DACH4
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0035
DACH5
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0036
DACH6
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0037
-
-
-
-
-
-
-
-
-
$0038
DACH7
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$0039
DACH8
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$003A
DACH9
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$003B
DACH10
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$003C
DACH11
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
$003D
DACH12
80H
DKVL7
DKVL6
DKVL5
DKVL4
DKVL3
DKVL2
DKVL1
DKVL0
RW
DAC control register ($000F) and DAC value register ($0030 - $003D)
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