參數(shù)資料
型號(hào)： NT6828
廠商： Electronic Theatre Controls, Inc.
英文描述： I2C Bus Controlled On-Screen Display
中文描述： I2C總線控制屏幕顯示
文件頁(yè)數(shù)： 16/31頁(yè)
文件大小： 1846K
代理商： NT6828
NT6828
16
(10) Row 15, Column 18:
7
6
5
4
3
2
1
0
Row 15
Column 18
FBKGOP PWMCTRL DBOUNCE HPOL
VPOL VCO1 VCO0
OSD Screen Control 2
Bit 6: FBKGOP
- This bit selects the polarity of the output signal of FBKG pin. This signal is active low when the user
clears this bit. Otherwise, active high set this bits. The default value is ‘1’ after power-on. Please refer to Figure 7
for the FBKGOP control timing.
Bit 5: PWMCTRL
- This bit selects the output option to PWM/HFTON pin. This bit will enable the PWM output as it is set
to ‘1’. Otherwise, it will select the HFTON option. The default value is ‘0’ after power-on. Please refer to Figure 7 for
the HFTON O/P timing and refer to Figure 8 PWMCLK O/P timing.
Bit 4: DBOUNCE
- This bit activates the debounce circuit of horizontal and vertical scan. It prevents from the OSD screen
shaking when the user adjusts the horizontal phase or vertical position. This bit is cleared after power-on.
Bit 3: HPOL
- This bit selects the polarity of the input signal of horizontal sync (HFLB pin). If the input sync signal has
negative polarity, the user must clear this bit. Otherwise, set this bit to ‘1’ to accept a positive polarity signal. After
power-on, this bit is cleared to ‘0’ and it will accept a negative polarity sync signal.
Bit 2: VPOL
- This bit selects the polarity of the input signal of vertical sync (VFLB pin). If the input sync signal is negative
polarity, the user must clear this bit. Otherwise, set this bit to ‘1’ to accept the positive polarity signal. After power-
on, this bit is cleared to ‘0’ and it will accept a negative polarity sync signal.
Bit 1 - 0: VCO1/0-
These bits select the VCO frequency range when the user sets the horizontal display resolution
flexibly. It is related to the horizontal display resolution and the user must set the control register at row15 /
column15 properly. The default value is VCO1 = 0 & VCO0 = 0 after power-on state. The relationship between
VCO1/0 and display resolution is listed as follows:
P.R. (Pixel Rate) = HDR * 12 * Freq
HFLB
Table 6. VCO Section & Freq. Limitation
Section
VCO1
VCO0 VCO Freq. Min VCO Freq. Max
Unit
P.R. Limit
HFLB Freq. Limit
Freq1
0
0
6
12
Freq2
0
1
12
24
Freq3
1
0
24
48
Freq4
1
1
48
92.2
MHz
Min < P.R. < Max
( Min / HDR*12 ) <
Freq
< Max / ( HDR*12 )
If there are no signals at HFLB input, the PLL will generate an approximate 1.8 MHz clock to ensure the proper operation of
the I2C bus and other control registers.
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