參數(shù)資料
型號(hào)： NT6828
廠商： Electronic Theatre Controls, Inc.
英文描述： I2C Bus Controlled On-Screen Display
中文描述： I2C總線控制屏幕顯示
文件頁(yè)數(shù)： 15/31頁(yè)
文件大?。?/td> 1846K
代理商： NT6828
NT6828
15
(7) Flexible Display Control Register: Row 15, Column 15
7
6
5
4
3
2
1
0
HDR
Row 15
Column 15
MSB
LSB
Horizontal Display Resolution Control
Bit 6 - 0: HDR
- These bits determine the resolution of horizontal display line. The unit of this setting is 12 dots
(1 character). With a total of 92, the user can adjust the resolution from 36 to 127 characters on each horizontal
line steps ($24 - $7F: 36 - 127 steps; note that its value can not be smaller than 36 at any given time.) Also
make a special note that the resolution adjustment must be joined together with the VCO setting at row15 /
column18 control register. The default value is 40 after power-on.
(Please refer to the Table showing the control register at row15 / column18.)
(8) OSD Row to Row Space Control Register: Row 15, Column 16
7
6
5
4
3
2
1
0
R2RSPACE
Row 15
Column 16
MSB
LSB
Row To Row Space Adjustment
Bit 4 - 0: R2RSPACE
- These bits define the row to row spacing in unit of horizontal line. It means extra lines, defined by
this 5-bit value, will be appended for each display row. The default value of it is 0 after power-on and there is no
any extra line inserted between each row.
(9) Input/Output Control Register: Row 15, Column 17
7
6
5
4
3
2
1
0
Row 15
Column 17
OSDEN BSEN
SHADOW
RGBF
BLANK CLRWIN CLRDSPR FBKGC
OSD Screen Control 1
Bit 7: OSDEN
- This bit will enable the OSD circuit as it is set to ‘1’. The default value is ‘0’ after power-on.
Bit 6: BSEN
- This bit will enable the bordering and shadowing effect as it is set to ‘1’. The default value of this bit is ‘0’
after power-on.
Bit 5: SHADOW
- When the BSEN is set to ‘1’, it will enable the shadowing effect as this bit set to ‘1’. Otherwise, it will
enable the bordering effect as this bit cleared to ‘0’. The default value is ‘0’ after power-on. (Please refer to Figure
6)
Bit 4: RGBF
- This bit controls the driving state of the output pins, R, G, B and FBKG when the OSD is disabled. After
power-on, this bit is cleared to ‘0’ and all of the R, G, B and FBKG pins output at high impedance state while the
OSD being disabled. If this bit is set to ‘1’, these R, G, B pins will drive low while OSD is being disabled, but the
FBKG pins will output ‘0’ if the FBKGP bit is set to ‘1’, whereas output ‘1’, set to ‘0’.
Bit 3: BLANK-
This bit will force the FBKG pin to output high as it is set to ‘1’. The default value of this bit is ‘0’ after
power-on.
Bit 2: CLRWIN-
This bit will clear all of windows’ WINEN control bit as it is set to ‘1’. The default value of this bit is ‘0’
after power-on.
Bit 1: CLRDSPR-
This bit will clear all of the contents in the display registers as it is set to ‘1’. The default value of this bit
is ‘0’ after power-on.
Bit 0: FBKGC
This bit determines the configuration of FBKG output pin. When it is cleared, the FBKG pin will output high
while displaying characters or windows. Otherwise, it will output high only while displaying characters. The default
value is ‘0’ after power-on. Please refer to Figure 7 for the FBKG O/P timing.
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NT6861U 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller for Monitor
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