參數(shù)資料
型號(hào)： NT5SV32M8AT-7K
廠商： Electronic Theatre Controls, Inc.
英文描述： 256Mb Synchronous DRAM
中文描述： 256Mb的同步DRAM
文件頁(yè)數(shù)： 15/65頁(yè)
文件大?。?/td> 814K
代理商： NT5SV32M8AT-7K
NT5SV64M4AT(L)
NT5SV32M8AT(L)
NT5SV16M16AT(L)
256Mb Synchronous DRAM
REV 1.0
May, 2001
15
NANYA TECHNOLOGY CORP
. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs
must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data
contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is pre-
sented on the DQ pins before the Read Command is initiated will actually be written to the memory.
Minimum Write to Read Interval
COMMAND
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
t
CK2
,
DQs
CAS latency = 2
DIN A
0
t
CK3
,
DQs
CAS latency = 3
DIN A
0
CK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
(Burst Length = 4, CAS latency = 2, 3)
: “H” or “L”
相關(guān)PDF資料
PDF描述
NT5SV32M8AT-8B 256Mb Synchronous DRAM
NT5SV64M4AT 256Mb Synchronous DRAM
NT5SV64M4AT-7K 256Mb Synchronous DRAM
NT5SV64M4AT-8B 256Mb Synchronous DRAM
NT5SV64M4AT-75B 256Mb Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NT5SV32M8AT-8B 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:256Mb Synchronous DRAM
NT5SV4M16DT 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:64Mb Synchronous DRAM
NT5SV4M16DT-6K 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:64Mb Synchronous DRAM
NT5SV4M16DT-7 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:64Mb Synchronous DRAM
NT5SV4M16DT7K 制造商:Nanya Technology Corporation 功能描述:
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