- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363668 > NT256D64S8HA0G-75B (Electronic Theatre Controls, Inc.) 184pin Two Bank Unbuffered DDR SDRAM MODULE PDF資料下載
參數(shù)資料
| 型號： | NT256D64S8HA0G-75B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 184pin Two Bank Unbuffered DDR SDRAM MODULE |
| 中文描述： | 184pin兩個銀行無緩沖DDR SDRAM內(nèi)存模塊 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 203K |
| 代理商： | NT256D64S8HA0G-75B |
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Operating, Standby, and Refresh Currents
Preliminary
8
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
( T
A
= 0 °C ~ 70 °C ; V
DDQ
= 2.5V ± 0.2V; V
DD
= 2.5V ± 0.2V, See AC Characteristics)
Symbol
Parameter/Condition
PC1600
PC2100
Unit
Notes
I
DD0
Operating Current : one bank; active / precharge; t
RC
= t
RC (MIN)
;
t
CK
= t
CK (MIN)
; DQ, DM, and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating Current : one bank; active / read / precharge; Burst = 2;
t
RC
= t
RC (MIN)
; CL=2.5; t
CK
= t
CK (MIN)
; I
OUT
= 0mA;
address and control inputs changing once per clock cycle
Precharge Power-Down Standby Current :
all banks idle; power-down mode; CKE
≤
V
IL (MAX)
; t
CK
= t
CK (MIN)
Idle Standby Current :
CS
≥
V
IH (MIN)
; all banks idle; CKE >= V
IH(MIN)
;
t
CK
= t
CK (MIN)
; address and control inputs changing once per clock cycle
Active Power-Down Standby Current : one bank active;
power-down mode; CKE
≤
V
IL (MAX)
; t
CK
= t
CK (MIN)
Active Standby Current : one bank; active / precharge; CS
≥
V
IH (MIN)
;
CKE
≥
V
IH (MIN)
; t
RC
= t
RAS (MAX)
; t
CK
= t
CK (MIN)
; DQ, DM, and DQS
inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating Current :
one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS outputs changing twice per clock cycle; CL = 2.5;
t
CK
= t
CK (MIN)
; I
OUT
= 0mA
Operating Current : one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
DQ and DQS inputs changing twice per clock cycle; CL=2.5;
t
CK
= t
CK (MIN)
1000
1160
mA
1,2
I
DD1
1120
1360
mA
1,2
I
DD2P
240
240
mA
1,2
I
DD2N
480
560
mA
1,2
I
DD3P
240
240
mA
1,2
I
DD3N
800
960
mA
1,2
I
DD4R
1640
1800
mA
1,2
I
DD4W
1320
1680
mA
1,2
t
RC
= t
RFC (MIN)
t
RC
= 15.625 μs
1840
252
2400
252
mA
mA
1,2
1,2,4
I
DD5
Auto-Refresh Current :
I
DD6
1. I
DD
specifications are tested after the device is properly initialized.
2. Input slew rate = 1V/ ns .
3. Enables on-chip refresh and address counters.
4. Current at 15.625 μs is time averaged value of I
DD5
at t
RFC (MIN)
and I
DD2P
over 15.625 μs.
Self-Refresh Current : CKE
≤
.2V
32
32
mA
1,2,3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NT256D64S8HA0G-7K | 184pin Two Bank Unbuffered DDR SDRAM MODULE |
| NT256D64S8HA0G-8B | 184pin Two Bank Unbuffered DDR SDRAM MODULE |
| NT3881D | Dot Matrix LCD Controller and Driver |
| NT3881DF-01 | Dot Matrix LCD Controller and Driver |
| NT3881DF-02 | Dot Matrix LCD Controller and Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT256D64S8HA0G-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin Two Bank Unbuffered DDR SDRAM MODULE |
| NT256D64S8HA0G-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin Two Bank Unbuffered DDR SDRAM MODULE |
| NT256D64SH8B0GM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:200pin Unbuffered DDR SO-DIMM |
| NT256D64SH8B0GM-75B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:200pin Unbuffered DDR SO-DIMM |
| NT256D72S890G-5T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184 pin Unbuffered DDR DIMM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。