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參數(shù)資料
| 型號： | NT256D64S8HA0G-75B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 184pin Two Bank Unbuffered DDR SDRAM MODULE |
| 中文描述： | 184pin兩個銀行無緩沖DDR SDRAM內(nèi)存模塊 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 203K |
| 代理商： | NT256D64S8HA0G-75B |
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
AC Timing Specification Notes
1. Input slew rate = 1V/ns.
2. The CK/
CK
input reference level (for timing reference to CK/
CK
) is the point at which CK and
CK
cross: the input reference level for
signals other than CK/
CK
, is V
REF
.
3. Inputs are not recognized as valid until V
REF
stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V
TT
.
5. t
HZ
and t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW,
or transitioning from high to low at this time, depending on tDQSS .
8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between V
OH
(AC) and V
OL
(AC).
10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between V
OH
(AC) and V
OL
(AC).
11. CK/
CK
slew rates are >= 1.0 V/ns.
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester characterization.
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system
clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5.
Preliminary
11
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns.
Input Slew Rate
elta ( t
IS )
Delta ( t
IH )
Unit
Note
0.5 V/ns
0
0
ps
1,2
0.4 V/ns
+50
0
ps
1,2
0.3 V/ns
+100
0
ps
1,2
1. Input slew rate is based on the lesser of the slew rates determined by either V
IH (AC)
to V
IL (AC)
or V
IH (DC)
to V
IL (DC)
, similarly
for rising transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns.
Input Slew Rate
Delta ( t
DS )
Delta ( t
DH )
Unit
Note
0.5 V/ns
0
0
ps
1,2
0.4 V/ns
+75
+75
ps
1,2
0.3 V/ns
+150
+150
ps
1,2
1. I/O slew rate is based on the lesser of the slew rates determined by either V
IH (AC)
to V
IL (AC)
or V
IH (DC)
to V
IL (DC)
, similarly for
rising transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ.
Delta Rise and Fall Rate
Delta ( t
DS )
Delta ( t
DH )
Unit
Note
0.0 ns/V
0
0
ps
1,2,3,4
0.25 ns/V
+50
+50
ps
1,2,3,4
0.5 ns/V
+100
+100
ps
1,2,3,4
1. Input slew rate is based on the lesser of the slew rates determined by either V
IH (AC)
to V
IL (AC)
or V
IH (DC)
to V
IL (DC)
, similarly
for rising transitions.
2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V
Using the table above, this would result in an increase in t
DS
and t
DH
of 100 ps.
4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each
device.
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| NT256D64S8HA0G-8B | 184pin Two Bank Unbuffered DDR SDRAM MODULE |
| NT3881D | Dot Matrix LCD Controller and Driver |
| NT3881DF-01 | Dot Matrix LCD Controller and Driver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT256D64S8HA0G-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin Two Bank Unbuffered DDR SDRAM MODULE |
| NT256D64S8HA0G-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin Two Bank Unbuffered DDR SDRAM MODULE |
| NT256D64SH8B0GM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:200pin Unbuffered DDR SO-DIMM |
| NT256D64SH8B0GM-75B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:200pin Unbuffered DDR SO-DIMM |
| NT256D72S890G-5T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184 pin Unbuffered DDR DIMM |
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