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參數(shù)資料
| 型號： | NT256D64S8HA0G-75B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 184pin Two Bank Unbuffered DDR SDRAM MODULE |
| 中文描述： | 184pin兩個銀行無緩沖DDR SDRAM內(nèi)存模塊 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 203K |
| 代理商： | NT256D64S8HA0G-75B |
NT256D64S8HA0G
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DIMM
Serial Presence Detect
32Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 2.5V DDR SDRAMs with SPD
Preliminary
12
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
-7K
-75
80
08
07
0C
0A
02
40
00
04
70
75
75
75
00
80
08
00
Byte
Description
-7K
-75B
128
256
-8B
-8B
Note
0
1
2
3
4
5
6.
7
8
9
10
11
12
13
14
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Bank
Data Width of Assembly
Data Width of Assembly (cont’)
Voltage Interface Level of this Assembly
SDRAM Device Cycle Time at CL=2.5
SDRAM Device Access Time from Clock at CL=2.5
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Width
Error Checking SDRAM Device Width
SDRAM Device Attributes :
Minimum Clock Delay, Random Column Access
SDRAM Device Attributes: Burst Length Supported
SDRAM Device Attributes: Number of Device Banks
SDRAM Device Attributes:
CAS
Latency
SDRAM Device Attributes:
CS
Latency
SDRAM Device Attributes: WE Latency
SDRAM Module Attributes
SDRAM Device Attributes: General
Minimum Clock Cycle at CL=2
Maximum Data Access Time from Clock at CL=2
Minimum Clock Cycle Time at CL=1
Maximum Data Access Time from Clock at CL=1
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse Width (t
RAS
)
Module Bank Density
Address and Command Setup Time Before Clock
Address and Command Hold Time After Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
Reserved
SPD Revision
Checksum Data
Manufacturer’s JEDED ID Code
Module Manufacturing Location
Module Part number
Module Revision Code
Module Manufacturing Data
Module Serial Number
99-255 Reserved
1.
yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex)
2.
ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)
SDRAM DDR
12
10
2
X64
X64
SSTL 2.5V
7.5ns
0.75ns
0.75ns
Non-Parity
15.6μs / SR
7ns
8ns
0.8ns
80
80
X8
N/A
15
1 Clock
01
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
2,4,8
4
2, 2.5
0
1
0E
04
0C
01
02
20
00
A0
75
00
00
50
3C
50
2D
20
90
90
50
50
00
00
9D
2, 2.5
2, 2.5
0C
0C
Differential Clock
+/-0.2V Voltage Tolerance
7.5ns
10ns
± 0.75ns ± 0.75ns ± 0.8ns
N/A
N/A
20ns
20ns
15ns
15ns
20ns
20ns
45ns
45ns
128MB
0.9ns
0.9ns
0.9ns
0.9ns
0.5ns
0.5ns
0.5ns
0.5ns
Undefined
0
0
0B
N/A
N/A
N/A
N/A
Year / Week Code
Serial Number
Undefined
10ns
75
75
A0
80
20ns
15ns
20ns
50ns
50
3C
50
2D
50
3C
50
32
1.1ns
1.1ns
0.6ns
0.6ns
90
90
50
50
B0
B0
60
60
36-61
62
63
64-71
72
73-90
91-92
93-94
95-98
0
00
6D
7F7F7F0B00000000
00
00
00
00
yy/ww
00
00
00
23
N/A
00
1,2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT256D64S8HA0G-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin Two Bank Unbuffered DDR SDRAM MODULE |
| NT256D64S8HA0G-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin Two Bank Unbuffered DDR SDRAM MODULE |
| NT256D64SH8B0GM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:200pin Unbuffered DDR SO-DIMM |
| NT256D64SH8B0GM-75B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:200pin Unbuffered DDR SO-DIMM |
| NT256D72S890G-5T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184 pin Unbuffered DDR DIMM |
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