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參數(shù)資料
| 型號(hào)： | NT256D64S88A2GM-8B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 200pin One Bank Unbuffered DDR SO-DIMM |
| 中文描述： | 200pin一個(gè)銀行緩沖的DDR SO - DIMM插槽 |
| 文件頁(yè)數(shù)： | 9/14頁(yè) |
| 文件大?。?/td> | 210K |
| 代理商： | NT256D64S88A2GM-8B |
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NT256D64S88A2GM
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DDR SO-DIMM
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating
Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to V SS .
2. Tests for AC timing, IDD , and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but
the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and I DD tests may use a V
IL
to V
IH
swing of up to 1.5V in the test environment, but input timing is still referenced to V
REF
(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals is 1V/ns in the range between V
IL(AC)
and V
IH(AC)
unless otherwise specified.
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the
signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW
(HIGH) level.
AC Output Load Circuits
Preliminary
01 / 2002
9
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Timing Reference Point
V
TT
50 ohms
30 pF
Output
V
OUT
AC Operating Conditions
( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)
Symbol
V
IH(AC)
V
IL(AC)
V
ID(AC)
V
IX(AC)
1. Input slew rate = 1V/ ns .
2. Inputs are not recognized as valid until V
REF
stabilizes.
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK.
4. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the same.
Parameter/Condition
Min
Max
Unit
V
V
V
V
Notes
1, 2
1, 2
1, 2, 3
1, 2, 4
Input High (Logic 1) Voltage.
Input Low (Logic 0) Voltage.
Input Differential Voltage, CK and
CK
Inputs
Input Differential Pair Cross Point Voltage, CK and
CK
Inputs
V
REF
+ 0.31
0.62
(0.5*V
DDQ
) - 0.2
V
REF
0.31
V
DDQ
+ 0.6
(0.5*V
DDQ
) +0.2
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| NT256D64S88AAG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin One Bank Unbuffered DDR SDRAM MODULE |
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| NT256D64S88ABG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin One Bank Unbuffered DDR SDRAM MODULE |
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