- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363668 > NT256D64S88A2GM-75B (Electronic Theatre Controls, Inc.) 200pin One Bank Unbuffered DDR SO-DIMM PDF資料下載
參數(shù)資料
| 型號： | NT256D64S88A2GM-75B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 200pin One Bank Unbuffered DDR SO-DIMM |
| 中文描述： | 200pin一個銀行緩沖的DDR SO - DIMM插槽 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 210K |
| 代理商： | NT256D64S88A2GM-75B |
NT256D64S88A2GM
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DDR SO-DIMM
Serial Presence Detect --
Part 1 of 2
Preliminary
01 / 2002
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
SPD Entry Value
DDR266B
-75B
Serial PD Data Entry (Hexadecimal)
DDR266A
-7K
-75
Note
Byte
Description
DDR266A
-7K
DDR200
-8B
DDR266B
DDR200
-8B
0
Number of Serial PD Bytes Written during
Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Bank
Data Width of Assembly
Data Width of Assembly (cont’)
Voltage Interface Level of this Assembly
DDR SDRAM Device Cycle Time at CL=2.5
DDR SDRAM Device Access Time from
Clock at CL=2.5
DIMM Configuration Type
Refresh Rate/Type
Primary DDR SDRAM Width
Error Checking DDR SDRAM Device Width
DDR SDRAM Device Attr: Min CLk Delay,
Random Col Access
DDR SDRAM Device Attributes:
Burst Length Supported
DDR SDRAM Device Attributes: Number of
Device Banks
DDR SDRAM Device Attributes: CAS
Latencies Supported
DDR SDRAM Device Attributes: CS Latency
DDR SDRAM Device Attributes: WE Latency
DDR SDRAM Device Attributes:
DDR SDRAM Device Attributes: General
Minimum Clock Cycle at CL=2
Maximum Data Access Time from Clock at
CL=2
Minimum Clock Cycle Time at CL=1
Maximum Data Access Time from Clock at
CL=1
Minimum Row Precharge Time(t
RP
)
Minimum Row Active to Row Active delay
(t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse Width (t
RAS
)
Module Bank Density
Address and Command Setup Time Before
Clock
Address and Command Hold Time After
Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
Reserved
SPD Revision
Checksum Data
128
80
1
2
3
4
5
6.
7
8
9
256
08
07
0D
0A
01
40
00
04
75
SDRAM DDR
13
10
1
X64
X64
SSTL 2.5V
7.5ns
7ns
8ns
70
80
10
0.75ns
0.75ns
0.8ns
75
75
80
11
12
13
14
Non-Parity
SR/1x(7.8us)
X8
N/A
00
82
08
00
15
1 Clock
01
16
2,4,8
0E
17
4
04
18
2/2.5
2/2.5
2/2.5
0C
0C
0C
19
20
21
22
23
0
1
01
02
20
00
A0
Differential Clock
+/-0.2V Voltage Tolerance
7.5ns
10ns
10ns
75
A0
24
0.75ns
0.75ns
0.8ns
75
75
80
25
N/A
00
26
N/A
00
27
20ns
20ns
20ns
50
50
50
28
15ns
15ns
15ns
3C
3C
3C
29
30
31
20ns
45ns
20ns
45ns
256MB
20ns
50ns
50
2D
50
2D
40
50
32
32
0.9ns
0.9ns
1.1ns
90
90
B0
33
0.9ns
0.9ns
1.1ns
90
90
B0
34
35
0.5ns
0.5ns
0.5ns
0.5ns
Undefined
Initial
0.6ns
0.6ns
50
50
50
50
00
00
BF
60
60
36-61
62
63
Initial
Initial
00
8F
00
45
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NT256D64S88A2GM-7K | 200pin One Bank Unbuffered DDR SO-DIMM |
| NT256D64S88A2GM-8B | 200pin One Bank Unbuffered DDR SO-DIMM |
| NT256D64S8HA0G-6 | 184pin Two Bank Unbuffered DDR SDRAM MODULE |
| NT256D64S8HA0G | 184pin Two Bank Unbuffered DDR SDRAM MODULE |
| NT256D64S8HA0G-75B | 184pin Two Bank Unbuffered DDR SDRAM MODULE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NT256D64S88A2GM-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:200pin One Bank Unbuffered DDR SO-DIMM |
| NT256D64S88A2GM-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:200pin One Bank Unbuffered DDR SO-DIMM |
| NT256D64S88AAG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin One Bank Unbuffered DDR SDRAM MODULE |
| NT256D64S88AAG-75B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin One Bank Unbuffered DDR SDRAM MODULE |
| NT256D64S88AAG-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:184pin One Bank Unbuffered DDR SDRAM MODULE |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。