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參數(shù)資料
| 型號： | NSD-2101 |
| 廠商： | AUSTRIAMICROSYSTEMS AG |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | SQUIGGLE? Motor Driver; Package Type: QFN(4x4)-16 |
| 封裝： | QFN(4x4)-16 |
| 文件頁數(shù)： | 15/22頁 |
| 文件大?。?/td> | 486K |
| 代理商： | NSD-2101 |
15 - 22
NSD-2101
Datasheet - Application Information
8.1 Integration with SQL-RV-1.8 SQUIGGLE Motor
Communicating with the NSD-2101.
The address of the NSD-2101 is 54h (unless the ADR pin is held high in which case the address would be 55h).
I2C supports 8 data bits and 1 acknowledge bit for a total of 9 bits or clock cycles per byte. When attempting to select a device, the first byte
transmtted by the master contains the device address. This address occupies the upper 7 data bits with data bit 0 having a value of zero which
indicates a write operation (theNSD-2101 does not support a read operation).
Therefore when addressing the NSD-2101 the actual value sent by the host during the first 8 SCL (clock) cycles would be A8h (or AAh if ADR pin
high). If the NSD-2101 is powered and connected properly to the SDA/SCL lines then on the 9th clock pulse, the NSD-2101 will hold the data line
low (acknowledge).
The second byte transmtted must be the number of the register to be written. For example, if attempting to send a pulse count, then the register
value would be 2.
The third and any subsequent bytes are the values to be written to the specified register and, if more than three bytes are being sent, the
following registers in increasing order.
If the following data were sent over the I2C bus:
A80277FF
Then registers 02 and 03 of the NSD-2101 would receive values of 77h and FFh respectively.
Supporting More Than Two NSD-2101s on a Single I2C Bus.
To support more than two NSD-2101 drivers on the same I2C bus, the ADR pin may be used as a chip select. That is, one driver is held low by
the host and on all others it is held high. The host then sends commands to the driver with ADR held low This of course requires that there be a
separate chip select line for each NSD-2101.
How Motion is Generated.
Motion is initiated by directing the NSD-2101 to issue pulses to the motor. In the case of the SQL-RV-1.8 motor, to get any motion, the interval
between the start of each pulse (i.e. the period) must be within some tolerance (e.g. ±2KHz) of the resonant frequency of the motor (e.g. ~172
kHz).
The closer this period is to the resonant frequency of the motor, the more speed/push force is available. Keep in mnd that this is a friction drive
which means the amount of motion is dependent on supply voltage, applied frequency vs. actual resonant frequency and the load on the motor.
Froman idle state, a mnimumof 5 to 10 pulses are required to build up enough orbital motion (of the nut about the screw) to advance the screw
The mnimumpulse count varies with load (higher load, more pulses) and whether or not motion is against or with the load (more against, fewer
with).
As shown in
Figure3
, the drive signal is composed of two waveforms (square waves) and each waveformmay be full or half bridge. In the case
of the SQL motor, these waveforms are 90 degrees out of phase (in keeping with the geometry of the nut). The phase that leads determnes the
direction of motion (direction is set by the host using a bit fromthe pulse count register).
By default the pulse width of each waveformis 50% of the period (i.e. if register 04 is zero; e.g. pulse with would be 2.9 μsec if the period is 5.8
μsec). But you can adjust the pulse width as one means to regulate speed. The shorter the pulse width (below 50% of the period), the less time
the piezo has to change shape and thus the amount of engagement between nut and screw is reduced.
The default phase shift between waveforms is 25% of the period (i.e. if register 05 is zero). This can also be adjusted and would be for other
motor geometries but in the case of the SQL-RV-1.8; 25% is recommended.
A second means to adjust speed is to set the ratio of full bridge pulses to half bridge pulses (Hybrid Speed Control). This effectively sets the
average voltage seen by the motor. If the supply is 3V then in full bridge the motor “sees” 6V. But if the hybrid speed is 33% then, on an average,
the motor sees 4V.
Note:
Due to dissipation limtations of the driver chip, the maximumsupply voltage for full bridge operation is 4.5V (9V to the piezo). Although
the driver supports a supply of up to 5.5V, at any level above 4.5V, the output needs to be half bridge. Within that limtation the hybrid
speed control is more power efficient than the pulse width control method of the regulating speed since the amount of switching into the
capacitive load of the motor is being reduced.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NSD-2101_07 | 制造商:AMSCO 制造商全稱:austriamicrosystems AG 功能描述:Piezo Motor Driver ASIC for SQL-RV Series Reduced Voltage SQUIGGLE RV and UTAF Motors |
| NSD-2101-ASST | 功能描述:IC DRIVER MOTOR SQUIGGLE 16-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電機和風(fēng)扇控制器，驅(qū)動器 系列:SQUIGGLE® 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:步進電機驅(qū)動器，1-2 相，2 相 評估套件:- 輸出數(shù):1 電流 - 輸出:800mA 電壓 - 負(fù)載:10 V ~ 28 V 電源電壓:4.75 V ~ 5.25 V 工作溫度:-20°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:28-SOP + 2 翼片裸露焊盤 供應(yīng)商設(shè)備封裝:28-HSOPHC（15.2x7.9） 包裝:剪切帶 (CT) 其它名稱:869-1268-1 |
| NSD2101-DQFS | 制造商:AMSCO 制造商全稱:austriamicrosystems AG 功能描述:Piezo Motor Driver ASIC for SQL-RV Series Reduced Voltage SQUIGGLE RV and UTAF Motors |
| NSD2101-DWLS | 制造商:AMSCO 制造商全稱:austriamicrosystems AG 功能描述:Piezo Motor Driver ASIC for SQL-RV Series Reduced Voltage SQUIGGLE RV and UTAF Motors |
| NSD225 | 制造商:Microsemi Corporation 功能描述:BAE PN 3274989-7,REVJ - Bulk |
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