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參數(shù)資料
| 型號(hào)： | NM27P040QM150 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PROM |
| 英文描述： | 4,194,304-Bit (512K x 8) Processor Oriented CMOS EPROM |
| 中文描述： | 512K X 8 UVPROM, 150 ns, CDIP32 |
| 封裝： | WINDOWED, CERAMIC, DIP-32 |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大?。?/td> | 151K |
| 代理商： | NM27P040QM150 |
Functional Description
DEVICE OPERATION
The six modes of operation of the EPROM are listed in Ta-
ble I. It should be noted that all inputs for the six modes are
at TTL levels. The power supplies required are V
CC
and
V
PP
. The V
PP
power supply must be at 12.75V during the
three programming modes, and must be at 5V in the other
three modes. The V
CC
power supply must be at 6.25V dur-
ing the three programming modes, and at 5V in the other
three modes.
Read Mode
The EPROM has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE/PGM) is the power control and should be
used for device selection. Output Enable (OE) is the output
control and should be used to gate data to the output pins,
independent of device selection. Assuming that addresses
are stable, address access time (t
ACC
) is equal to the delay
from CE to output (t
CE
). Data is available at the outputs t
OE
after the falling edge of OE, assuming that CE/PGM has
been low and addresses have been stable for at least t
ACC
-
t
OE
.
Standby Mode
The EPROM has a standby mode which reduces the active
power dissipation by over 99%, from of 165 mW to
0.55 mW. The EPROM is placed in the standby mode by
applying a CMOS high signal to the CE/PGM input. When in
standby mode, the outputs are in a high impedance state,
independent of the OE input.
Output Disable
The EPROM is placed in output disable by applying a TTL
high signal to the OE input. When in output disable all cir-
cuitry is enabled, except the outputs are in a high imped-
ance state (TRI-STATE).
Output OR-Typing
Because the EPROM is usually used in larger memory ar-
rays, National has provided a 2-line control function that
accommodates this use of multiple memory connections.
The 2-line control function allows for:
a) the lowest possible memory power dissipation, and
b) complete assurance that output bus contention will not
occur.
To most efficiently use these two control lines, it is recom-
mended that CE/PGM be decoded and used as the primary
device selecting function, while OE be made a common
connection to all devices in the array and connected to the
READ line from the system control bus. This assures that all
deselected memory devices are in their low power standby
modes and that the output pins are active only when data is
desired from a particular memory device.
Programming
CAUTION: Exceeding 14V on pin 1 (V
PP
) will damage the
EPROM.
Initially, and after each erasure, all bits of the EPROM are in
the ‘‘1’s’’ state. Data is introduced by selectively program-
ming ‘‘0’s’’ into the desired bit locations. Although only
‘‘0’s’’ will be programmed, both ‘‘1’s’’ and ‘‘0’s’’ can be pre-
sented in the data word. The only way to change a ‘‘0’’ to a
‘‘1’’ is by ultraviolet light erasure.
The EPROM is in the programming mode when the V
PP
power supply is at 12.75V and OE is at V
IH
. It is required
that at least a 0.1
m
F capacitor be placed across V
PP
, V
CC
to ground to suppress spurious voltage transients which
may damage the device. The data to be programmed is
applied 8 bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.
When the address and data are stable, an active low, TTL
program pulse is applied to the CE/PGM input. A program
pulse must be applied at each address location to be pro-
grammed. The EPROM is programmed with the Fast Pro-
gramming Algorithm shown in Figure 1. Each Address is
programmed with a series of 100
m
s pulses until it verifies
good, up to a maximum of 25 pulses. Most memory cells will
program with a single 100
m
s pulse.
The EPROM must not be programmed with a DC signal ap-
plied to the CE/PGM input.
Programming multiple EPROM in parallel with the same
data can be easily accomplished due to the simplicity of the
programming requirements. Like inputs of the parallel
EPROM may be connected together when they are pro-
grammed with the same data. A low level TTL pulse applied
to the CE/PGM input programs the paralleled EPROM.
Program Inhibit
Programming multiple EPROMs in parallel with different
data is also easily accomplished. Except for CE/PGM all
like inputs (including OE) of the parallel EPROMs may be
common. A TTL low level program pulse applied to an
EPROM’s CE/PGM input with V
PP
at 12.75V will program
that EPROM. A TTL high level CE/PGM input inhibits the
other EPROMs from being programmed.
Program Verify
A verify should be performed on the programmed bits to
determine whether they were correctly programmed. The
verify may be performed with V
PP
at 12.75V. V
PP
must be at
V
CC
, except during programming and program verify.
AFTER PROGRAMMING
Opaque labels should be placed over the EPROM window
to prevent unintentional erasure. Covering the window will
also prevent temporary functional failure due to the genera-
tion of photo currents.
MANUFACTURER’S IDENTIFICATION CODE
The EPROM has a manufacturer’s identification code to aid
in programming. When the device is inserted in an EPROM
programmer socket, the programmer reads the code and
then automatically calls up the specific programming algo-
rithm for the part. This automatic programming control is
only possible with programmers which have the capability of
reading the code.
The Manufacturer’s Identification code, shown in Table II,
specifically identifies the manufacturer and device type. The
code for NM27P040 is ‘‘8F08’’, where ‘‘8F’’ designates that
8
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