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參數(shù)資料
| 型號： | NCV7510DWR2 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | FlexMOS Programmable Peak and Hold PWM MOSFET Predriver |
| 中文描述： | FlexMOS可編程峰值和保持MOSFET的預(yù)驅(qū)動器的PWM |
| 文件頁數(shù)： | 15/22頁 |
| 文件大小： | 160K |
| 代理商： | NCV7510DWR2 |
NCV7510
http://onsemi.com
15
DETAILED OPERATING DESCRIPTION (continued)
Bits D
5
and D
4
program the respective antisaturation
detection thresholds for the GATE (high side) and CLAMP
MOSFETs. At POR, the GATE threshold is nominally set to
1.2 V and the CLAMP to 0.4 V. Programming the respective
bits to 1 nominally sets the GATE threshold to 2.4 V and the
CLAMP to 0.8 V.
Bit D
3
selects the functional mode for the PCLK input. At
POR, D
3
=0 and the PCLK input is configured to accept a
clock signal as the time base for an internal programmable
dwell timer. The dwell timer determines when to change
modes from peak to hold. Setting D
3
=1 configures the
PCLK input to accept a logiclevel input which then directly
controls the selection of the peak or hold mode. When D
3
=1,
PCLK=0 selects the peak mode and PCLK=1 selects the
hold mode.
Bits D
2
D
0
program the dwell timer prescaler to divide
the incoming clock signal at the PCLK input when AUX bit
D
3
=0. Refer to the Dwell Timer register description for
additional programming details.
Peak/Hold DAC Registers [$10,$08,$04,$02]
The peak and hold registers program the DAC reference
pairs for the peak and hold load currents. Each 8bit register
uses only the 7 lower bits, and bit 8 must always be set to 0.
At POR, the registers are set to $00.
The PKHI ($10) and PKLO ($08) register pair contents
are the DAC reference values used during the peak mode of
the control cycle. The HDHI ($04) and HDLO ($02) register
pair contents are the DAC reference values used during the
hold mode of the control cycle. The peak or hold mode is
determined by the state of the internal dwell timer or the
logic level at the PCLK input. Refer to the AUX register and
Dwell Timer register descriptions for additional details. The
register values for the load currents can be determined with
the following equation:
IL
4.92 mV
VAL10
RSNS
LSBs
(eq. 1)
where I
L
is the desired load current, R
SNS
is the current sense
resistor, and 4.92 mV is the nominal D/A resolution. The
maximum value of load current that can be programmed for
a given R
SNS
resistor can be found by:
IL(MAX)
625 mV
RSNS
(eq. 2)
where 625 mV is the nominal D/A fullscale value.
Dwell Time Register [$20]
The 8bit dwell timer register value determines when the
programmed DAC reference pairs change from the peak
mode to the hold mode. Dwell timer operation is also
dependant upon the value of AUX register bits D
3
D
0
(refer
to the Auxiliary register description.) Figure 14 shows a
detailed block diagram of the dwell timer.
8bit
Down Counter
÷
20
3bit
Prescale
Divider
PCLK
Peak
Dwell
Time
(10
μ
S Time Base)
$01
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
$20
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
420MHz Clock
Figure 14. Dwell Timer Block Diagram
When AUX D
3
=0, the dwell timer register value is
combined with the AUX D
2
D
0
prescale value to generate
a dwell time based on the clock signal applied to the PCLK
input. The timer is designed to produce dwell times from 0
to 2.55 ms with 10 s resolution for popular host controller
clock rates. Figure 15 illustrates the prescale divisor truth
table for some common clock rates.
$01
D
7
D
3
D
2
D
1
D
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
X
D
6
D
5
D
4
÷
2
÷
3
÷
4
÷
5
÷
6
÷
7
÷
8
÷
10
DIRECT IN
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
PCLK (MHz)
4.0
6.0
8.0
10.0
12.0
14.0
16.0
20.0
Logic Level
Figure 15. AUX Register Prescale Divisors
A general formula for determining dwell time based on
the clock frequency applied to the PCLK input is:
(DIV
tDWELL
20
N10)
20
PCLK
(eq. 3)
where t
DWELL
is the dwell time in s, DIV is the prescale
divisor, PCLK is the clock frequency in MHz, and N
is the
content of the DWELL time register.
Fault Reporting
When a fault occurs, the opendrain FAULT flag is
latched low and fault information is latched and transferred
into the SPI shift register while CSB is high.
The host controller initiates SPI communication when
CSB goes low, and current fault information can then be
shifted out of the NCV7510’s SO output. While CSB is low,
transfer of new fault information is blocked. The FAULT
flag and fault data are cleared by the rising edge of CSB.
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