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參數(shù)資料
| 型號(hào)： | NCV7510DWR2 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | FlexMOS Programmable Peak and Hold PWM MOSFET Predriver |
| 中文描述： | FlexMOS可編程峰值和保持MOSFET的預(yù)驅(qū)動(dòng)器的PWM |
| 文件頁(yè)數(shù)： | 14/22頁(yè) |
| 文件大小： | 160K |
| 代理商： | NCV7510DWR2 |
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NCV7510
http://onsemi.com
14
DETAILED OPERATING DESCRIPTION
Power Up/Down Control
The NCV7510 powerup control prevents spurious output
operation by interlocking the V
BAT
and V
DD
power
supplies. At the system level, it is assumed that the V
BAT
voltage is available before the V
DD
voltage. The PowerOn
Reset (POR) interlock circuit derives an output disable
signal from the V
BAT
voltage at the DRN input and causes
the GATE and CLAMP outputs to be kept at the PGND
potential. Application of the V
DD
power supply allows the
outputs to subsequently be enabled when the V
DD
voltage
exceeds the POR threshold. All internal registers are then
initialized to their default states, fault data is cleared and the
GATE and CLAMP outputs are held low (external MOSFET
V
GS
approximately 0 V.) When the V
DD
voltage falls below
the POR threshold during power down, the GATE and
CLAMP outputs are driven and held low until V
BAT
falls
below about 1.2 volts.
SPI Communication
The NCV7510 is a 16bit SPI slave device.
Fault data is
simultaneously sent from the device’s SO pin while
command data is received at the SI pin under synchronous
control of the master’s SCLK signal. No parity or buffer
under/over run detection circuitry is employed; therefore a
valid CSB frame must contain exactly 16 SCLK cycles for
each CSB high–low–high transition.
The host initiates communication when the CSB input is
driven low. Present fault data is latched in the device’s SPI
shift register when CSB goes low. Fault data, sent MSB first
at the SO output, changes on the falling edge of SCLK and
is guaranteed valid before the next rising edge of SCLK. The
data at the SI input is received MSB first and must be valid
before the rising edge of SCLK. The 16 bits received at the
SI input before CSB is driven high will be translated as the
current command.
SPI communication between the host and the NCV7510
may either be parallel via individual CSB addressing or
daisychained through other devices using a compatible SPI
protocol.
Command and Register Structure
The 16bit command data received by the NCV7510 is
decoded into 8bit address and 8bit data words. The upper
byte, beginning with the received MSB, is bitwise decoded
to address one of six internal registers and the lower byte is
decoded into program data for the addressed register. A
dummy address ($00) can also be sent to retrieve fault data.
Note that the register addresses are not fully decoded.
Sending an address combining more than one address bit
will result in the same data being sent to more than one
register. Bits A
7
and A
6
select internal test modes and should
always be set to 0. Figure 12 describes the general 16bit SPI
word format and valid register addresses. Each register is
next described in detail.
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
$01 AUX
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
$02 HDLO
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
$04 HDHI
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
$08 PKLO
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
$10 PKHI
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
$20 DWELL
MSB
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
LSB
ADDRESS
DATA
Figure 12. 16bit SPI Word Format and Valid Register
Addresses
Auxiliary Register [$01]
The AUX register is used to program several diagnostic
features and the behavior of the dwell timer under control of
the PCLK input and the DWELL timer register. This
register is initialized to $00 at POR. Bit definitions are
shown for this register in Figure 13.
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
$01 AUX
DWELL TIME PRESCALE
PCLK INPUT MODE
CLAMP ANTISAT THRESHOLD
GATE ANTISAT THRESHOLD
OVERVOLTAGE ENABLE
Figure 13. AUX Register Bit Definitions
Bit D
7
selects an internal test mode and should always be
set to 0. Bit D
6
controls
interruption of load current by the
overvoltage detection function. At POR, the overvoltage
interrupt function is disabled. Programming D
6
=1 enables
overvoltage interrupt and will cause the FAULT output to
respond to an overvoltage event. Overvoltage events are
reported via the SPI shift register regardless of the state of
AUX D
6
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NCV7510DWR2G | 功能描述:功率驅(qū)動(dòng)器IC OSPI PRE-DRIVER RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| NCV7512 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:FLEXMOS Quad Low-Side Pre-Driver |
| NCV7512FTG | 功能描述:功率驅(qū)動(dòng)器IC ANA HEX LO-SD PREDRV RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| NCV7512FTR2G | 功能描述:功率驅(qū)動(dòng)器IC ANA HEX LO-SD PREDRV RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube |
| NCV7513 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:FLEXMOS Hex Low−Side MOSFET Pre−Driver |
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