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參數(shù)資料
| 型號： | NCP5423DR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Dual Out−of−Phase Synchronous Buck Controller with Current Limit |
| 中文描述： | 1.5 A DUAL SWITCHING CONTROLLER, 750 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | LEAD FREE, SOP-16 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 171K |
| 代理商： | NCP5423DR2G |
NCP5422A, NCP5423
http://onsemi.com
9
Figure 6. Hiccup Overcurrent Protection
Output Enable
On/Off control of the regulator outputs can be
implemented by pulling the COMP pins low. The COMP
pins must be driven below the 0.425 V PWM comparator
offset voltage in order to disable the switching of the GATE
drivers.
DESIGN GUIDELINES
Definition of the design specifications
The output voltage tolerance can be affected by any or all
of the following reasons:
1. buck regulator output voltage setpoint accuracy;
2. output voltage change due to discharging or charging
of the bulk decoupling capacitors during a load
current transient;
3. output voltage change due to the ESR and ESL of the
bulk and high frequency decoupling capacitors,
circuit traces, and vias;
4. output voltage ripple and noise.
Budgeting the tolerance is left up to the designer who must
take into account all of the above effects and provide an
output voltage that will meet the specified tolerance at the
load.
The designer must also ensure that the regulator
component temperatures are kept within the manufacturer’s
specified ratings at full load and maximum ambient
temperature.
Selecting Feedback Divider Resistors
V
OUT
R1
R2
V
FB
Figure 7. Selecting Feedback Divider Resistors
Selection of Feedback Divider Resistors
Feedback divider resistors R1 and R2 are selected based
on a design tradeoff between efficiency and output voltage
accuracy. Both error amplifiers are referenced to 1.0 V, and
resistors R1 and R2 are connected from each channel’s
output voltage to the inverting pin (V
FB1(2)
) of each error
amplifier. To set the channel output voltage, first choose a
value for R1, and then R2 can be sized as follows:
R1
Vout
1.0
1
R2
The output voltage error due to the bias current of the error
amplifier and the parallel combination of R1 and R2 can now
be estimated:
1.6 · 106·R1
Error
R2
Reducing the size of R1 and R2 will reduce the output
voltage error, but increase the power dissipation.
Calculating Duty Cycle
The duty cycle of a buck converter (including parasitic
losses) is given by the formula:
Duty Cycle
D
VOUT
VIN
VLFET
VL
VLFET
VHFET
where:
V
OUT
= buck regulator output voltage;
V
HFET
= high side FET voltage drop due to R
DS(ON)
;
V
L
= output inductor voltage drop due to inductor wire
DC resistance;
V
IN
= buck regulator input voltage;
V
LFET
= low side FET voltage drop due to R
DS(ON)
.
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| NCP5424AD | 功能描述:IC REG CTRLR BUCK PWM 16-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:4,000 系列:- PWM 型:電壓模式 輸出數(shù):1 頻率 - 最大:1.5MHz 占空比:66.7% 電源電壓:4.75 V ~ 5.25 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 85°C 封裝/外殼:40-VFQFN 裸露焊盤 包裝:帶卷 (TR) |
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