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參數(shù)資料
| 型號： | NCP5423DR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Dual Out−of−Phase Synchronous Buck Controller with Current Limit |
| 中文描述： | 1.5 A DUAL SWITCHING CONTROLLER, 750 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | LEAD FREE, SOP-16 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 171K |
| 代理商： | NCP5423DR2G |
NCP5422A, NCP5423
http://onsemi.com
12
The minimum inductance value for the input inductor is
therefore:
LIN
V
(dI dt)MAX
where:
L
IN
= input inductor value;
V = voltage seen by the input inductor during a full load
swing;
(dI/dt)
MAX
= maximum allowable input current slew rate.
The designer must select the LC filter pole frequency so
that at least 40 dB attenuation is obtained at the regulator
switching frequency. The LC filter is a doublepole network
with a slope of 2.0, a rolloff rate of 40 dB/dec, and a
corner frequency:
fC
1
2
LC
where:
L = input inductor;
C = input capacitor(s).
SELECTION OF THE POWER FETS
FET Basics
The use of the MOSFET as a power switch is propelled by
two reasons: 1)
Its very high input impedance
; and 2)
Its very
fast switching times
. The electrical characteristics of a
MOSFET are considered to be those of a perfect switch.
Control and drive circuitry power is therefore reduced.
Because the input impedance is so high, it is voltage driven.
The input of the MOSFET acts as if it were a small capacitor,
which the driving circuit must charge at turn on. The lower
the drive impedance, the higher the rate of rise of V
GS
, and
the faster the turnon time. Power dissipation in the
switching MOSFET consists of 1) conduction losses, 2)
leakage losses, 3) turnon switching losses, 4) turnoff
switching losses, and 5) gatetransitions losses. The latter
three losses are proportional to frequency.
The most important aspect of FET performance is the
Static DrainToSource OnResistance (R
DS(ON)
), which
affects regulator efficiency and FET thermal management
requirements. The OnResistance determines the amount of
current a FET can handle without excessive power
dissipation that may cause overheating and potentially
catastrophic failure. As the drain current rises, especially
above the continuous rating, the OnResistance also
increases. Its positive temperature coefficient is between
+0.6%/
°
C and +0.85%/
°
C. The higher the OnResistance
the larger the conduction loss is. Additionally, the FET gate
charge should be low in order to minimize switching losses
and reduce power dissipation.
Both logic level and standard FETs can be used.
Voltage applied to the FET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the FET gates
will be driven railtorail due to overshoot caused by the
capacitive load they present to the controller IC.
Selection of the Switching (Upper) FET
The designer must ensure that the total power dissipation
in the FET switch does not cause the power component to
exceed it’s maximum rating.
The maximum RMS current through the switch can be
determined by the following formula:
IRMS(H)
IL(PEAK)2
IL(VALLEY)2
(IL(PEAK)
IL(VALLEY))
D
3
where:
I
RMS(H)
= maximum switching MOSFET RMS current;
I
L(PEAK)
= inductor peak current;
I
L(VALLEY)
= inductor valley current;
D = duty cycle.
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated:
IRMS(H)2
where:
P
RMS(H)
= switching MOSFET conduction losses;
I
RMS(H)
= maximum switching MOSFET RMS current;
R
DS(ON)
= FET draintosource onresistance
The upper MOSFET switching losses are caused during
MOSFET switchon and switchoff and can be determined
by using the following formula:
PSWH
PSWH(ON)
VIN
IOUT
PRMS(H)
RDS(ON)
PSWH(OFF)
(tRISE
6T
tFALL)
where:
P
SWH(ON)
= upper MOSFET switchon losses;
P
SWH(OFF)
= upper MOSFET switchoff losses;
V
IN
= input voltage;
I
OUT
= load current;
t
RISE
= MOSFET rise time (from FET manufacturer’s
switching characteristics performance curve);
t
FALL
= MOSFET fall time (from FET manufacturer’s
switching characteristics performance curve);
T = 1/f
SW
= period.
The total power dissipation in the switching MOSFET can
then be calculated as:
PHFET(TOTAL)
PRMS(H)
where:
P
HFET(TOTAL)
= total switching (upper) MOSFET losses;
P
RMS(H)
= upper MOSFET switch conduction Losses;
P
SWH(ON)
= upper MOSFET switchon losses;
P
SWH(OFF)
= upper MOSFET switchoff losses;
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature can
be calculated:
PSWH(ON)
PSWH(OFF)
TJ
TA
[PHFET(TOTAL)
RJA]
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