- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361102 > NCP5331FTR2 (ON SEMICONDUCTOR) Two-Phase PWM Controller with Integrated Gate Drivers PDF資料下載
參數(shù)資料
| 型號： | NCP5331FTR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Two-Phase PWM Controller with Integrated Gate Drivers |
| 中文描述： | 1.5 A SWITCHING CONTROLLER, 750 kHz SWITCHING FREQ-MAX, PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 9/38頁 |
| 文件大?。?/td> | 424K |
| 代理商： | NCP5331FTR2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
NCP5331
http://onsemi.com
9
PACKAGE PIN DESCRIPTION
Pin No.
Symbol
Description
1
V
FB
Voltage Feedback Pin. To use Adaptive Voltage Positioning (AVP), set the light load offset voltage
by connecting a resistor between V
FB
and V
CORE
. The resistor and the V
FB
bias current determine
the offset. For no adaptive positioning connect V
FB
directly to V
CORE
.
2
V
DRP
Current sense output for Adaptive Voltage Positioning (AVP). The offset of this pin above the DAC
voltage is proportional to the output current. Connect a resistor from this pin to V
FB
to set the
amount AVP or leave this pin open for no AVP. This pin’s maximum working voltage is 4.1 Vdc.
3
LGND
Return for the internal control circuits and the IC substrate connection.
4, 6
CS1, CS2
Current sense inputs. Connect the current sense network for the corresponding phase to each in-
put. The input voltages to these pins must be kept within 125 mV of CS
REF
.
5
CS
REF
Reference for both differential current sense amplifiers. To balance input offset voltages between
the inverting and non-inverting inputs of the Current Sense Amplifiers, connect this pin to the output
voltage through a resistor equal to one third of the value of the current sense resistors.
7
V
FFB
Fast Feedback connection to the PWM comparators and input to the Power Good comparator.
8
5 V
REF
Reference output. Decouple to LGND with 0.1
μ
F.
9
R
OSC
A resistor from this pin to ground sets the operating frequency and V
FB
bias current.
10
-SEN
Ground connection for the DAC. Provides remote sensing of ground at the load.
11-15
VID pins
Voltage ID DAC inputs. These pins are internally pulled up and clamped at 2.3 V if left unconnected.
16
V
CCL2
Power for GL2.
17
GL2
Low side driver #2.
18
GND2
Return for driver #2.
19
GH2
High side driver #2.
20
V
CCH
Power for GH1 and GH2.
21
CB
OUT
Open-collector crowbar output pin. This pin is high impedance when an overvoltage condition is
detected at CS
REF
. Connect this pin to the gate of a MOSFET or SCR to crowbar either V
CORE
or
V
IN
to GND. To prevent failure of the crowbar device, this pin should be used in conjunction with
logic on the motherboard to disable the ATX supply via PS
ON
and/or a relatively fast fuse should be
placed upstream to disconnect the input voltage.
22
GH1
High side driver #1.
23
GND1
Return for driver #1.
24
GL1
Low side driver #1.
25
V
CCL1
Power for GL1.
26
V
CCL
Power for the internal control circuits. UVLO sense for Logic connects to this pin.
27
C
OVC
A capacitor from this pin to ground sets the time the controller will be in hiccup mode current limit.
This timer is started by the first overcurrent condition (set by the I
LIM
voltage). Once timed out, volt-
age at the V
CCL
pin must be cycled to reset this fault. Connecting this pin to LGND
±
200 mV will
disable this function and hiccup mode current limit will operate indefinitely.
28
C
PGD
A capacitor from this pin to ground sets the programmable time between when V
CORE
crosses the
PWRGD threshold and when the open-collector PWRGD pin transitions from a logic Low to a logic
High. The minimum delay is internally set to 200
μ
s. Connecting this pin to 5 V
REF
will disable the
programmable timer and the delay will be set to the internal delay.
29
PGD
Power Good output. Open collector output that will transition Low when CS
REF
(V
CORE
) is out of
regulation.
30
5 V
SB
Input power for the CB
OUT
circuitry. To provide maximum overvoltage protection to the CPU, this pin
should be connected to 5 V
SB
from the ATX supply (ATX, pin 9). If the CB
OUT
function is not used,
this pin must be connected to the NCP5331 controller’s internal voltage reference (5 V
REF
, pin 8).
31
I
LIM
Sets the threshold for current limit. Connect to reference through a resistive divider. This pin’s maxi-
mum working voltage is 3.0 Vdc.
32
COMP
Output of the error amplifier and input for the PWM comparators.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NCP5383 | Two Phase Buck Controller with Integrated Gate Drivers and AVP |
| NCP5422ADR2G | Dual Out−of−Phase Synchronous Buck Controller with Current Limit |
| NCP5423 | Dual Out−of−Phase Synchronous Buck Controller with Current Limit |
| NCP5423DR2G | Dual Out−of−Phase Synchronous Buck Controller with Current Limit |
| NCP5424DG | Dual Synchronous Buck Controller with Input Current Sharing |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NCP5331FTR2G | 功能描述:DC/DC 開關(guān)控制器 2 Phase Buck w/Gate Drivers for Athlon RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| NCP5332A | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two-Phase Buck Controller with Integrated Gate Drivers and 5-Bit DAC |
| NCP5332A/D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two-Phase Buck Controller with Integrated Gate Drivers and 5-Bit DAC |
| NCP5332ADW | 功能描述:DC/DC 開關(guān)控制器 2 Phase Buck w/Gate RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| NCP5332ADWR2 | 功能描述:DC/DC 開關(guān)控制器 2 Phase Buck w/Gate RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。