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參數(shù)資料
| 型號： | NCP5331FTR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Two-Phase PWM Controller with Integrated Gate Drivers |
| 中文描述： | 1.5 A SWITCHING CONTROLLER, 750 kHz SWITCHING FREQ-MAX, PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 23/38頁 |
| 文件大?。?/td> | 424K |
| 代理商： | NCP5331FTR2 |
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NCP5331
http://onsemi.com
23
Layout Guidelines
With the fast rise, high output currents of microprocessor
applications, parasitic inductance and resistance should be
considered when laying out the power, filter and feedback
signal sections of the board. Typically, a multilayer board
with at least one ground plane is recommended. If the layout
is such that high currents can exist in the ground plane
underneath the controller or control circuitry, the ground
plane can be slotted to route the currents away from the
controller. The slots should typically not be placed between
the controller and the output voltage or in the return path of
the gate drive. Additional power and ground planes or
islands can be added as required for a particular layout.
Gate drives experience high di/dt during switching and the
inductance of gate drive traces should be minimized. Gate
drive traces should be kept as short and wide as practical and
should have a return path directly below the gate trace.
Output filter components should be placed on wide planes
connected directly to the load to minimize resistive drops
during heavy loads and inductive drops and ringing during
transients. If required, the planes for the output voltage and
return can be interleaved to minimize inductance between
the filter and load.
The current sense signals are typically tens of millivolts.
Noise pick-up should be avoided wherever possible.
Current feedback traces should be routed away from noisy
areas such as the switch node and gate drive signals. If the
current signals are taken from a location other than directly
at the inductor any additional resistance between the
pick-off point and the inductor appears as part of the
inherent inductor resistances and should be considered in
design calculations. The capacitors for the current feedback
networks should be placed as close to the current sense pins
as practical. After placing the NCP5331 control IC, follow
these guidelines to optimize the layout and routing:
1. Place the 1
μ
F ceramic power-supply bypass
capacitors close to their associated pins: V
CCL
,
V
CCH
, V
CCL1
and V
CCL2
.
2. Place the MOSFETs to minimize the length of the
Gate traces. Orient the MOSFETs such that the
Drain connections are away from the controller and
the Gate connections are closest to the controller.
3. Place the components associated with the internal
error amplifier (R
F1
, C
F1
, C
C1
, C
C2
, R
C1
, C
A1
,
R
DRP
) to minimize the trace lengths to the pins
V
FB
, V
DRP
and COMP.
4. Place the current sense components (R
S1
, R
S2
,
C
S1
, C
S2
, R
S
, C
SA
, C
SB
) near the CS1, CS2, and
CS
REF
pins.
5. Place the frequency setting resistor (R
OSC
) close to
the R
OSC
pin. The R
OSC
pin is very sensitive to
noise. Route noisy traces, such as the SWNODEs
and GATE traces, away from the R
OSC
pin and
resistor.
6. Place the MOSFETs and output inductors to
reduce the size of the noisy SWNODEs. However,
there is a trade-off between reducing the size of
the SWNODEs for noise reduction and providing
adequate heat-sinking for the synchronous
MOSFETs.
7. Place the input inductor and input capacitor(s) near
the Drain of the control (upper) MOSFETs. There
is a trade-off between reducing the size of this
node to save board area and providing adequate
heat-sinking for the control (upper) MOSFETs.
8. Place the output capacitors (electrolytic and
ceramic) close to the processor socket or output
connector.
9. The trace from the SWNODEs to the current sense
components (R
S1
, R
S2
) will be very noisy. Route
this away from more sensitive, low-level traces.
The Ground layer can be used to help isolate this
trace.
10. The Gate traces are very noisy. Route these away
from more sensitive, low-level traces. Try to keep
each Gate signal on one layer and insure that there
is an uninterrupted return path directly below the
Gate trace. The Ground layer can be used to help
isolate these traces.
11. Gate driver returns, GND1 and GND2, should not
be connected to LGND, but instead directly to the
ground plane.
12. Try not to “daisy chain” connections to Ground
from one via. Ideally, each connection to Ground
will have its own via located as close to the
component as possible.
13. Use a slot in the ground plane to prevent high
currents from flowing beneath the control IC. This
slot should form an “island” for signal ground
under the control IC. “Signal ground” and “power
ground” must be separated. Examples of signal
ground include the capacitors at COMP, CS
REF
,
and 5V
REF
, the resistors at R
OSC
and I
LIM
, and the
LGND pin to the controller. Examples of power
ground include the capacitors to V
CCH
and V
CCL1
and V
CCL2
, the Source of the synchronous
MOSFETs, and the GND1 and GND2 pins of the
controller.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NCP5331FTR2G | 功能描述:DC/DC 開關(guān)控制器 2 Phase Buck w/Gate Drivers for Athlon RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| NCP5332A | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two-Phase Buck Controller with Integrated Gate Drivers and 5-Bit DAC |
| NCP5332A/D | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two-Phase Buck Controller with Integrated Gate Drivers and 5-Bit DAC |
| NCP5332ADW | 功能描述:DC/DC 開關(guān)控制器 2 Phase Buck w/Gate RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
| NCP5332ADWR2 | 功能描述:DC/DC 開關(guān)控制器 2 Phase Buck w/Gate RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK |
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