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參數(shù)資料
| 型號： | NCP5331FTR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Two-Phase PWM Controller with Integrated Gate Drivers |
| 中文描述： | 1.5 A SWITCHING CONTROLLER, 750 kHz SWITCHING FREQ-MAX, PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 26/38頁 |
| 文件大?。?/td> | 424K |
| 代理商： | NCP5331FTR2 |
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NCP5331
http://onsemi.com
26
+
+
Vi
12 V
Li
TBD
Ci
5
×
16MBZ1500M10X20
ESR
Ci
13 m/5 = 2.6 m
Q2
Q1
Lo
729 nH
ESR
Co
19 m/6 = 3.2 m
26 u(t)
Co
6
×
16MBZ1000M10X16
Vi(t = 0) = 12 V
SWNODE
Vo(t = 0) = 1.225 V
V
Ci
I
Lo
V
OUT
I
Li
MAX dI/dt occurs in
first few PWM cycles.
Figure 31. Calculating the Input Inductance
+
-
4. Input Inductor Selection
The use of an inductor between the input capacitors and
the power source will accomplish two objectives. First, it
will isolate the voltage source and the system from the noise
generated in the switching supply. Second, it will limit the
inrush current into the input capacitors at power up. Large
inrush currents will reduce the expected life of the input
capacitors. The inductor’s limiting effect on the input
current slew rate becomes increasingly beneficial during
load transients.
The worst case input current slew rate will occur during
the first few PWM cycles immediately after a step-load
change is applied as shown in Figure 31. When the load is
applied, the output voltage is pulled down very quickly.
Current through the output inductors will not change
instantaneously so the initial transient load current must be
conducted by the output capacitors. The output voltage will
step downward depending on the magnitude of the output
current (I
O,MAX
), the per capacitor ESR of the output
capacitors (ESR
OUT
), and the number of the output
capacitors (N
OUT
) as shown in Figure 31. Assuming the load
current is shared equally between the two phases, the output
voltage at full, transient load will be
VCORE,FULL- LOAD
VCORE,NO- LOAD
(14)
(IO,MAX2)
ESROUTNOUT
When the control MOSFET (Q1 in Figure 31) turns ON,
the input voltage will be applied to the opposite terminal of
the output inductor (the SWNODE). At that instant, the
voltage across the output inductor can be calculated as
VLo
VIN
VIN
VCORE,FULL- LOAD
VCORE,NO- LOAD
(IO,MAX2)
(15)
ESROUTNOUT
The differential voltage across the output inductor will
cause its current to increase linearly with time. The slew rate
of this current can be calculated from
dILodt
VLoLo
(16)
Current changes slowly in the input inductor so the input
capacitors must initially deliver the vast majority of the
input current. The amount of voltage drop across the input
capacitors (
V
Ci
) is determined by the number of input
capacitors (N
IN
), their per capacitor ESR (ESR
IN
), and the
current in the output inductor according to
ESRINNIN
ESRINNIN
VCi
dILodt
dILodt
tON
D fSW
(17)
Before the load is applied, the voltage across the input
inductor (V
Li
) is very small - the input capacitors charge to
the input voltage, V
IN
. After the load is applied the voltage
drop across the input capacitors,
V
Ci
, appears across the
input inductor as well. Knowing this, the minimum value of
the input inductor can be calculated from
VLi
VCi
LiMIN
dIINdtMAX
dIINdtMAX
(18)
where dI
IN
/dt
MAX
is the maximum allowable input current
slew rate.
The input inductance value calculated from Equation 18
is relatively conservative. It assumes the supply voltage is
very “stiff” and does not account for any parasitic elements
that will limit dI/dt such as stray inductance. Also, the ESR
values of the capacitors specified by the manufacturer’s data
sheets are worst case high limits. In reality input voltage
“sag,” lower capacitor ESRs, and stray inductance will help
reduce the slew rate of the input current.
As with the output inductor, the input inductor must
support the maximum current without saturating the
magnetic. Also, for an inexpensive iron powder core, such
as the -26 or -52 from Micrometals, the inductance “swing”
with dc bias must be taken into account - inductance will
decrease as the dc input current increases. At the maximum
input current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
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