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參數(shù)資料
| 型號： | NCP5306DW |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Three−Phase VRM 9.0 Buck Controller |
| 中文描述： | 0.1 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO24 |
| 封裝： | SOP-24 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 879K |
| 代理商： | NCP5306DW |
NCP5306
http://onsemi.com
19
As with the output inductor, the input inductor must
support the maximum current without saturating the
inductor. Also, for an inexpensive iron powder core, such as
the
26 or
52 from Micrometals, the inductance “swing”
with DC bias must be taken into account and inductance will
decrease as the DC input current increases. At the maximum
input current, the inductance must not decrease below the
minimum value or the dI/dt will be higher than expected.
5. MOSFET & Heatsink Selection
Power dissipation, package size and thermal requirements
drive MOSFET selection. To adequately size the heat sink,
the design must first predict the MOSFET power
dissipation. Once the dissipation is known, the heat sink
thermal impedance can be calculated to prevent the
specified maximum case or junction temperatures from
being exceeded at the highest ambient temperature. Power
dissipation has two primary contributors: conduction losses
and switching losses. The control or upper MOSFET will
display both switching and conduction losses. The
synchronous or lower MOSFET will exhibit only
conduction losses because it switches into nearly zero
voltage. However, the body diode in the synchronous
MOSFET will suffer diode losses during the non
overlap
time of the gate drivers.
For the upper or control MOSFET, the power dissipation
can be approximated from:
PD,CONTROL
(ILo,MAX
(Qoss2
(IRMS,CNTL2
QswitchIg
VIN
fSW)
RDS(on))
VIN
(VIN
fSW)
QRR
fSW)
(19)
The first term represents the conduction or IR losses when
the MOSFET is ON while the second term represents the
switching losses. The third term is the loss associated with
the
control and synchronous
MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous
MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
I
RMS,CNTL
is the RMS value of the trapezoidal current in
the control MOSFET:
(20)
IRMS,CNTL
[(ILo,MAX2
I
Lo,MAX
is the maximum output inductor current:
D
ILo,MAX
ILo,MIN
ILo,MIN2) 3]1 2
ILo,MAX
IO,MAX3
ILo2
(21)
I
Lo,MIN
is the minimum output inductor current:
ILo,MIN
IO,MAX3
ILo2
(22)
I
O,MAX
is the maximum converter output current.
I
D
V
GATE
V
DRAIN
Q
GD
Q
GS2
Q
GS1
V
GS_TH
Figure 23. MOSFET Switching Characteristics
D is the duty cycle of the converter:
D
VOUTVIN
(23)
Δ
I
Lo
is the peak
to
peak ripple current in the output
inductor of value L
o
:
ILo
(VIN
VOUT)
D (Lo
fSW)
(24)
R
DS(on)
is the ON resistance of the MOSFET at the
applied gate drive voltage.
Q
switch
is the post gate threshold portion of the
gate
to
source charge plus the gate
to
drain charge. This
may be specified in the data sheet or approximated from the
gate
charge curve as shown in the Figure 23.
Qswitch
Qgs2
Qgd
(25)
I
g
is the output current from the gate driver IC.
V
IN
is the input voltage to the converter.
f
sw
is the switching frequency of the converter.
Q
RR
is the reverse recovery charge of the
lower
MOSFET.
Q
oss
is the sum of all the MOSFET output charge specified
in the data sheet.
For the lower or synchronous MOSFET, the power
dissipation can be approximated from:
PD,SYNCH
(IRMS,SYNCH2
(Vfdiode
IO,MAX3
RDS(on))
t_nonoverlap
fSW)
(26)
The first term represents the conduction or IR losses when
the MOSFET is ON and the second term represents the diode
losses that occur during the gate non
overlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of:
(27)
IRMS,SYNCH
[(ILo,MAX2
1
D
ILo,MAX
ILo,MIN
ILo,MIN2) 3]1 2
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