參數(shù)資料
型號(hào)： NCP5306DW
廠商： ON SEMICONDUCTOR
元件分類： 穩(wěn)壓器
英文描述： Three−Phase VRM 9.0 Buck Controller
中文描述： 0.1 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO24
封裝： SOP-24
文件頁(yè)數(shù)： 14/24頁(yè)
文件大?。?/td> 879K
代理商： NCP5306DW
NCP5306
http://onsemi.com
14
Due to the faster than ideal RC time constant, there is an
overshoot of 50% and the overshoot decays with a 200
μ
s
time constant. With this compensation, the OCSET pin
threshold must be set more than 50% above the full load
current to avoid triggering current limit during a large output
load step.
Transient Response and Adaptive Voltage Positioning
For applications with fast transient currents, the output
filter is frequently sized larger than ripple currents require in
order to reduce voltage excursions during load transients.
Adaptive voltage positioning can reduce peak
peak output
voltage deviations during load transients and allow for a
smaller output filter. The output voltage can be set higher
than nominal at light loads to reduce output voltage sag
when the load current is applied. Similarly, the output
voltage can be set lower than nominal during heavy loads to
reduce overshoot when the load current is removed. For low
current applications, a droop resistor can provide fast,
accurate adaptive positioning. However, at high currents,
the loss in a droop resistor becomes excessive. For example,
a 50 A converter with a 1 m
Ω
resistor would provide a 50
mV change in output voltage between no load and full load
and would dissipate 2.5 W.
Lossless adaptive voltage positioning (AVP) is an
alternative to using a droop resistor, but it must respond to
changes in load current. Figure 18 shows how AVP works.
The waveform labeled “normal” shows a converter without
AVP. On the left, the output voltage sags when the output
current is stepped up and later overshoots when current is
stepped back down. With fast (ideal) AVP, the peak
to
peak
excursions are cut in half. In the slow AVP waveform, the
output voltage is not repositioned quickly enough after
current is stepped up and the upper limit is exceeded.
The controller can be configured to adjust the output
voltage based on the output current of the converter. (Refer
to the application diagram in Figure 1). To set the no
load
positioning, a resistor is placed between the output voltage
and V
FB
pin. The V
FB
bias current will develop a voltage
across the resistor to adjust the no
load output voltage. The
V
FB
bias current is dependent on the value of R
OSC
as shown
in the datasheets.
During no
load conditions, the V
DRP
pin is at the same
voltage as the V
FB
pin, so none of the V
FB
bias current flows
through the V
DRP
resistor. When output current increases,
the V
DRP
pin voltage increases proportionally. Current set
by the V
DRP
resistor offsets the V
FB
bias current, causing the
output voltage to decrease.
The response during the first few microseconds of a load
transient is controlled primarily by power stage output
impedance, and by the ESR and ESL of the output filter. The
transition between fast and slow positioning is controlled by
the total ramp size and the error amp compensation. If the
ramp size is too large or the error amp too slow, there will be
a long transition to the final voltage after a transient. This
will be most apparent with low capacitance output filters.
Figure 17. Inductive Sensing Waveform During a
Load Step with Fast RC Time Constant (50
μ
s/div)
Adaptive Positioning
Limits
Figure 18. Adaptive Voltage Positioning
Adaptive Positioning
Normal
Fast
Slow
Overvoltage Protection
Overvoltage protection (OVP) is provided as a result of
the normal operation of the Enhanced V
2
control topology
with synchronous rectifiers. The control loop responds to an
overvoltage condition within 40 ns, causing the GATEx
output to shut off. The (external) MOSFET driver should
react normally to turn off the top MOSFET and turn on the
bottom MOSFET. This results in a “crowbar” action to
clamp the output voltage and prevent damage to the load.
The regulator will remain in this state until the overvoltage
condition ends or the input voltage is pulled low.
Power Good
According to the latest specifications, the Power Good
(PWRGD) signal must be asserted when the output voltage
is within a window defined by the VID code, as shown in
Figure 19.
The PWRGDS pin is provided to allow the PWRGD
comparators to accurately sense the output voltage. The
effect of the PWRGD lower threshold can be modified using
a resistor divider from the output to PWRGDS to ground, as
shown in Figure 20.
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NCP5314_07 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two/Three/Four−Phase Buck CPU Controller
NCP5314FTR2 功能描述:IC CTRLR BUCK CPU 2/3/4PH 32LQFP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,000 系列:- 應(yīng)用:電源，ICERA E400，E450 輸入電壓:4.1 V ~ 5.5 V 輸出數(shù):10 輸出電壓:可編程 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:42-WFBGA，WLCSP 供應(yīng)商設(shè)備封裝:42-WLP 包裝:帶卷 (TR)
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