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參數(shù)資料
| 型號(hào)： | NCP5306 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | Three−Phase VRM 9.0 Buck Controller |
| 文件頁(yè)數(shù)： | 20/24頁(yè) |
| 文件大?。?/td> | 879K |
| 代理商： | NCP5306 |
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NCP5306
http://onsemi.com
20
where:
Vf
diode
is the forward voltage of the MOSFET’s intrinsic
diode at the converter output current.
t_nonoverlap is the non
overlap time between the upper
and lower gate drivers to prevent cross conduction.
This time is usually specified in the data sheet for the
control IC.
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature.
T
(TJ
TA) PD
(28)
where:
θ
T
is the total thermal impedance (
θ
JC
+
θ
SA
);
θ
JC
is the junction
to
case thermal impedance of the
MOSFET;
θ
SA
is the sink
to
ambient thermal impedance of the
heatsink assuming direct mounting of the MOSFET (no
thermal “pad” is used);
T
J
is the specified maximum allowed junction
temperature;
T
A
is the worst case ambient operating temperature.
For TO
220 and TO
263 packages, standard FR
4
copper clad circuit boards will have approximate thermal
resistances (
θ
SA
) as shown below:
Pad Size
(in
2
/mm
2
)
Single
Sided
1 oz. Copper
0.50/323
60
65
°
C/W
0.75/484
55
60
°
C/W
1.00/645
50
55
°
C/W
1.50/968
45
50
°
C/W
As with any power design, proper laboratory testing
should be performed to insure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow,
maximum input voltage, maximum loading and component
variations (i.e., worst case MOSFET R
DS(on)
). Also, the
inductors and capacitors share the MOSFET’s heatsinks and
will add heat and raise the temperature of the circuit board
and MOSFET. For any new design, it is advisable to have as
much heatsink area as possible. All too often, new designs are
found to be too hot and require re
design to add heatsinking.
6. Adaptive Voltage Positioning
There are two resistors that determine the Adaptive
Voltage Positioning: R
FB
and R
DRP
. R
FB
establishes the
no
load “high” voltage position and R
DRP
determines the
full
load “droop” voltage.
Resistor R
FB
is connected between V
CORE
and the V
FB
pin of the controller. At no load, this resistor will conduct the
internal bias current of the V
FB
pin and develop a voltage
drop from V
FB
to the V
CORE
pin. Because the error amplifier
regulates V
FB
to the DAC setting, the output voltage,
V
CORE
, will be lower by the amount IBIAS
VFB
R
FB
. This
condition is shown in Figure 24.
To calculate R
FB
, the designer must specify the no
load
voltage decrease below the VID setting (
Δ
V
NO
LOAD
) and
determine the V
FB
bias current. Usually, the no
load voltage
decrease is specified in the design guide for the processor
that is available from the manufacturer. The V
FB
bias current
is determined by the value of the resistor from R
OSC
to
ground (see Figure 4 in the data sheet for a graph of
IBIAS
VFB
versus R
OSC
). The value of R
FB
can then be
calculated:
RFB
VNO
LOADIBIASVFB
(29)
+
+
G
VDRP
Σ
R
CS1
CS1
C
CS1
L1
0 A
+
G
VDRP
R
CSx
CSx
C
CSx
Lx
0 A
CS
REF
COMP
Error
Amp
VID Setting
IBIAS
VFB
R
DRP
R
FB
V
DRP
= VID
V
FB
= VID
V
CORE
I
DRP
= 0
I
FB
= IBIAS
VFB
V
CORE
= VID + IBIAS
VFB
R
FB
Figure 24. AVP Circuitry at No
Load
+
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相關(guān)代理商/技術(shù)參數(shù) |
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| NCP5314 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Two/Three/Four-Phase Buck CPU Controller |
| NCP5314/D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Two/Three/Four-Phase Buck CPU Controller |
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