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NCP5306
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17
For decreasing current:
tDEC
Lo
IO(VOUT)
(3.2)
For typical processor applications with output voltages
less than half the input voltage, the current will be increased
much more quickly than it can be decreased. Thus, it may be
more difficult for the converter to stay within the regulation
limits when the load is removed than when it is applied and
excessive overshoot may result.
The output voltage ripple can be calculated using the
output inductor value derived in this Section (Lo
MIN
), the
number of output capacitors (N
OUT,MIN
) and the per
capacitor ESR determined in the previous Section:
VOUT,P
P
(ESR per cap
#Phases
NOUT,MIN)
D
(VIN
VOUT)
(LoMIN
fSW)
(4)
This formula assumes steady
state conditions with no
more than one phase on at any time. The second term in
Equation 4 is the total ripple current seen by the output
capacitors. The total output ripple current is the “time
summation” of the three individual phase currents that are
120 degrees out
of
phase. As the inductor current in one
phase ramps upward, current in the other phase ramps
downward and provides a canceling of currents during part
of the switching cycle. Therefore, the total output ripple
current and voltage are reduced in a multi
phase converter.
3. Input Capacitor Selection
The choice and number of input capacitors is primarily
determined by their voltage and ripple current ratings. The
designer must choose capacitors that will support the worst
case input voltage with adequate margin. To calculate the
number of input capacitors, one must first determine the
total RMS input ripple current. To this end, begin by
calculating the average input current to the converter:
IIN,AVG
IO,MAX
D
(5)
where:
D is the duty cycle of the converter, D = V
OUT
/V
IN
;
η
is the specified minimum efficiency;
I
O,MAX
is the maximum converter output current.
The input capacitors will discharge when the control FET
is ON and charge when the control FET is OFF as shown in
Figure 21.
The following equations will determine the maximum and
minimum currents delivered by the input capacitors:
IC,MAX
ILo,MAX
IIN,AVG
(6)
IC,MIN
ILo,MIN
IIN,AVG
(7)
I
Lo,MAX
is the maximum output inductor current:
ILo,MAX
IO,MAX3
ILo2
(8)
I
Lo,MIN
is the minimum output inductor current:
ILo,MIN
IO,MAX3
ILo2
(9)
Δ
I
Lo
is the peak
to
peak ripple current in the output
inductor of value Lo:
ILo
(VIN
VOUT)
D (Lo
fSW)
(10)
For the three
phase converter, the input capacitor(s) RMS
current is then:
ICIN,RMS
[3D
(IC,MIN2
IC,MIN
ILO
ILO23)
IIN,AVG2
(1
3D)]1 2
(11)
Select the number of input capacitors (N
IN
) to provide the
RMS input current (I
CIN,RMS
) based on the RMS ripple
current rating per capacitor (I
RMS,RATED
):
NIN
ICIN,RMSIRMS,RATED
(12)
For a three
phase converter with perfect efficiency (
η
= 1),
the worst case input ripple
current will occur when the
converter is operating at a 16.7% duty cycle. At this
operating point, the parallel combination of input capacitors
must support an RMS ripple current equal to 16.7% of the
converter’s DC output current. At other duty cycles, the
ripple
current will be less. For example, at a duty cycle of
either 3% or 30%, the three
phase input ripple
current will
be approximately 10% of the converter’s DC output current.
In general, capacitor manufacturers require derating to the
specified ripple
current based on the ambient temperature.
More capacitors will be required because of the current
derating. The designer should know the ESR of the input
capacitors. The input capacitor power loss can be calculated
from:
PCIN
ICIN,RMS2
ESR_per_capacitor NIN
(13)
Low ESR capacitors are recommended to minimize losses
and reduce capacitor heating. The life of an electrolytic
capacitor is reduced 50% for every 10
°
C rise in the
capacitor’s temperature.
I
C,MAX
I
C,MIN
0 A
I
IN,AVG
FET On,
Caps Discharging
FET Off,
Caps Charging
t
ON
T/3
Δ
I
C,IN
= I
C,MAX
I
C,MIN
=
Δ
I
LO
Figure 21. Input Capacitor Current for a
Four
Phase Converter