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NCP5214A
http://onsemi.com
23
Close loop system bandwidth can be calculated by:
R3
R1
VRAMP
Since the ramp amplitude of the PWM modulator has a
voltage feedforward function, the ramp amplitude is a
function of V
IN
which can be determined by:
VRAMP
1.25 V
Below are some guidelines for setting the compensation
components:
1. Set a value for R
1
between 2.0 k and 5.0 k .
2. Set a target for the close loop bandwidth which
should be less than 50% of the switching
frequency.
3. Pick compensation DC gain (R
3
/R
1
) for desired
close loop bandwidth.
4. Place 1st zero at half filter double pole.
5. Place 1st pole at ESR zero.
6. Place 2nd zero at filter double pole.
7. Place 2nd pole at half the switching frequency.
BW
VIN
1
2
L
COUT
(eq. 28)
0.045
(VIN5.0 V)
(eq. 29)
By using the above equations and guidelines, the
compensation components values can be determined by the
equations below:
R3
2
BW
VRAMP
R1
L
COUT
VIN
(eq. 30)
C2
2
L
COUT
R3
(eq. 31)
C1
C2
C2
COUT
R3
ESR
1
(eq. 32)
R4
R1
L
fSW
COUT
1
(eq. 33)
C3
1
R4
fSW
(eq. 34)
The modulator and filter gain, compensation gain, and
close loop gain asymptotic Bode plot can be drawn by the
calculated results to check the compensation gain and close
loop gain obtained. An example of asymptotic Bode plot is
shown in Figure 40.
The phase of the output filter can be calculated by:
Phase(Filter)
tan1(2 f
ESR
COUT)tan12 f
ESR
DCR
COUT
(2 f)2
L
COUT1
(eq. 35)
where the DCR of the inductor can be neglected if the DCR is small.
The phase of the Type III compensation network can be calculated by:
Phase(TypeIII)
90
°
tan1(2 f
R3
C2)tan12 f
R3
C1
C1
C3)
C2
C2
(eq. 36)
tan1(2 f
(R1
R4)
C3)tan1(2 f
R4
The close loop phase can be calculated by summing the
filter phase and compensation phase:
Phase(CloseLoop)
Phase(Filter)
Phase(TypeIII)
(eq. 37)
Then the close loop phase margin can be estimated by:
Phase(Margin)
Phase(CloseLoop)
( 180
°
)
(eq. 38)
It should be checked that closed loop gain has a 0 dB gain
crossing with 20 dB/decade slope and a phase margin of
45
°
or greater. The compensation components values may
require some adjustment to meet these requirements.
Besides, the compensation gain should be checked with the
error amplifier open loop gain to make sure that it is
bounded by the error amplifier open loop gain.
The poles and zeros locations and hence the
compensation network components values may need to be
further fine tuned after actual system testing and analysis.
Feedback Resistor Divider
The output voltage of the buck regulator can be adjusted
by the feedback resistor divider formed by R
1
and R
. Once
the value of R
1
is selected when determining the
compensation components, the value of R
2
can be obtained
by:
R2
0.8
VOUT0.8
R1
(eq. 39)
It is recommended to adjust the value of R
2
to finetune
the output voltage when it is necessary. The value of R
1
should not be changed since the compensation DC gain and
the 2
nd
zero break frequency of the compensation gain are
contributed by R
1
. If the value of R
1
is changed, the
compensation, the close loop bandwidth and phase margin,
and the system stability will be affected. Besides, it is
recommended to use resistors with at least 1% tolerance for
R
1
and R
2
.
SoftStart of Buck Regulator
A VDDQ softstart feature is incorporated in the device
to prevent surge current from power supply and output
voltage overshoot during power up. When VDDQEN,
VCCA, and VOCDDQ rise above their respective upper
threshold voltages, the external softstart capacitor C
SS
will be charged up by a constant current source, I
ss
. When
the softstart voltage (Vcss) rises above the SS_EN voltage
(
50 mV), the BGDDQ and TGDDQ will start switching
and VDDQ output will ramp up with VFBDDQ following
the softstart voltage. When the softstart voltage reaches
the SS_OK voltage (
Vref + 50 mV), the softstart of