參數(shù)資料
型號(hào)： NCP5214AMNR2G
廠商： ON SEMICONDUCTOR
元件分類： 穩(wěn)壓器
英文描述： 2−in−1 Notebook DDR Power Controller
中文描述： 3 A SWITCHING CONTROLLER, 460 kHz SWITCHING FREQ-MAX, DSO22
封裝： LEAD FREE, DFN-22
文件頁(yè)數(shù)： 21/31頁(yè)
文件大小： 376K
代理商： NCP5214AMNR2G
NCP5214A
http://onsemi.com
21
converter. Generally, highside MOSFET with R
DS(on)
about 7.0 m and lowside MOSFET with R
DS(on)
about
5.0 m can achieve good efficiency.
The maximum drain current rating of the highside
MOSFET and lowside MOSFET must be higher than the
peak inductor current at maximum load current. The
lowside MOSFET should have larger maximum drain
current rating than the highside MOSFET since the
lowside MOSFET have longer turnon time.
The maximum draintosource voltage rating of the
MOSFETs used in buck converter should be at least 1.2 times
of the maximum input voltage. Generally, V
DSS
of 30 V
should be sufficient for both highside MOSFET and
lowside MOSFET of the buck converter for notebook
application.
As a general rule of thumb, the gate charges are the
smaller; the better is the MOSFET while R
DS(on)
is still low
enough. MOSFETs are susceptible to false turnon under
high dV/dt and high VDS conditions. Under high dV/dt and
high V
DS
condition, current will flow through the C
GD
of
the capacitor divider formed by C
GD
and C
GS
, cause the
C
GS
to charge up and the V
GS
to rise. If the V
GS
rises above
the threshold voltage, the MOSFET will turn on.
Therefore, it should be checked that the lowside MOSFET
have low Q
GD
to Q
GS
ratio. This indicates that the lowside
MOSFET have better immunity to short moment false
turnon due to high dV/dt during the turnon of the
highside MOSFET. Such short moment false turnon will
cause minor shootthrough current which will degrade
efficiency, especially at high input voltage condition.
Overcurrent Protection of VDDQ Buck Regulator
The OCP circuit is configured to set the current limit for
the current flowing through the highside FET and
inductor during S0 and S3. The overcurrent tripping level
is programmed by an external resistor RL1 connected
between the OCDDQ pin and drain of the highside FET.
An internal 31 A current sink (IOC) at pin OCDDQ
establishes a voltage drop across the resistor RL1 at a
magnitude of RL1xIOC and develops a voltage at the
noninverting input of the current limit comparator.
Another voltage drop is established across the highside
MOSFET R
DS(on)
at a magnitude of I
L
xR
DS(on)
and a
voltage is developed at SWDDQ when the highside
MOSFET is turned on and the inductor current flows
through the R
DS(on)
of the MOSFET. The voltage at the
noninverting input of the current limit comparator is then
compared to the voltage at SWDDQ pin when the
highside gate drive is high after a fixed period of blanking
time (150 ns) to avoid false current limit triggering. When
the voltage at SWDDQ is lower than the voltage at the
noninverting input of the current limit comparator for four
consecutive internal clock cycles, an overcurrent condition
occurs, during which, all outputs will be latched off to
protect against a shorttoground condition on SWDDQ or
VDDQ. i.e., the voltage drop across the R
DS(on)
of
highside FET developed by the drain current is larger than
the voltage drop across RL1, the OCP is triggered and the
device will be latched off.
The overcurrent protection will trip when a peak inductor
current hit the I
LIMIT
determined by the equation:
RL1
ILIMIT
IOC
RDS(on)
(eq. 19)
It should be noted that the OCDDQ pin must be pulled
high to VIN through a resistor RL1 and this pin cannot be
left floating for normal operation. The voltage drop across
RL1 must be less than 1.0 V to allow enough headroom for
the voltage detection at the OCDDQ pin under low VIN
condition. In addition, since the MOSFET R
DS(on)
varies
with temperature as current flows through the MOSFET
increases, the OCP trip point also varies with the MOSFET
R
DS(on)
temperature variation.
Since the IOC and R
DS(on)
have device variations and
MOSFET R
DS(on)
increase with temperature, to avoid false
triggering the overcurrent protection in normal operating
output load range, calculate the RL1 value from the
previous equation with the following conditions such that
minimum value of inductor current limit is set:
1. The minimum IOC value from the specification
table.
2. The maximum R
DS(on)
of the MOSFET used at
the highest junction temperature.
3. Determine I
LIMIT
for I
LIMIT
> I
LOAD(max)
+
I
L(ripple)/
2, where I
LOAD(max)
= I
VDDQ(max)
+
I
VTT(max)
if VTT is powered by VDDQ.
Besides, a decoupling capacitor C
DCPL
should be added
closed to the lead of the current limit setting resistor RL1
which connected to the drain of the highside MOSFET.
Loop Compensation
Once the output LC filter components have been
determined, the compensation network components can be
selected. Since NCP5214A is a voltage mode PWM
converter with output LC filter, Type III compensation
network is required to obtain the desired close loop
bandwidth and phase boost with unconditional stability.
The NCP5214A PWM modulator, output LC filter and
Type III compensation network are shown in Figure 39.
The output LC filter has a double pole and a single zero.
The double pole is due to the inductance of the inductor and
capacitance of the output capacitor, while the single zero
is due to the ESR and capacitance of the output capacitor.
The Type III compensation has two RC polezero pairs.
The two zeros are used to compensate the LC double pole
and provide 180
°
phase boost. The two poles are used to
compensate the ESR zero and provide controlled gain
rolloff. For an ideally compensated system, the Bode plot
should have the closeloop gain rolloff with a slope of
20 dB/decade crossing the 0 dB with the required
bandwidth and the phase margin larger than 45
°
for all
frequencies below the 0 dB frequency. The closed loop
gain is obtained by adding the modulator and filter gain (in
dB) to the compensation gain (in dB)
.
The bandwidth is the
相關(guān)PDF資料
PDF描述
NCP5214 2-in-1 Notebook DDR Power Controller
NCP5214MNR2 2-in-1 Notebook DDR Power Controller
NCP5218 2−in−1 Notebook DDR Power Controller
NCP5218MNR2G 2−in−1 Notebook DDR Power Controller
NCP5220 3−in−1 PWM Dual Buck and Linear Power Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NCP5214EVB 功能描述:電源管理IC開(kāi)發(fā)工具 ANA NCP5214 EVAL BRD RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評(píng)估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V
NCP5214MNR2 功能描述:DC/DC 開(kāi)關(guān)控制器 2-IN-1 NOTBOOK DDR CNTLR RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開(kāi)關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
NCP5214MNR2G 功能描述:DC/DC 開(kāi)關(guān)控制器 2-IN-1 NOTBOOK DDR CNTLR RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開(kāi)關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
NCP5215 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Dual Synchronous Buck Controller for Notebook Power System
NCP5215MNR2G 功能描述:直流/直流開(kāi)關(guān)轉(zhuǎn)換器 BUCK CONTROLLER RoHS:否 制造商:STMicroelectronics 最大輸入電壓:4.5 V 開(kāi)關(guān)頻率:1.5 MHz 輸出電壓:4.6 V 輸出電流:250 mA 輸出端數(shù)量:2 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*