參數(shù)資料
型號: NCP1607BDR2G
廠商: ON Semiconductor
文件頁數(shù): 12/23頁
文件大?。?/td> 255K
描述: IC PFC CONTROLLER CRM 8SOIC
標(biāo)準(zhǔn)包裝: 1
模式: 臨界傳導(dǎo)(CRM)
電流 - 啟動: 23.5µA
電源電壓: 9.5 V ~ 20 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOICN
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: NCP1607BDR2GOSDKR
NCP1607
http://onsemi.com
12
A compensation network is placed between the FB and
Control pins to reduce the speed at which the EA responds
to changes in the boost output. This is necessary due to the
nature of an active PFC circuit. The PFC stage absorbs a
sinusoidal current from a sinusoidal line voltage. Hence,
the converter provides the load with a power that matches
the average demand only. Therefore, the output capacitor
must absorb the difference between the delivered power
and the power consumed by the load. This means that when
the power fed to the load is lower than the demand, the
output capacitor discharges to compensate for the lack of
power. Alternatively, when the supplied power is higher
than that absorbed by the load, the output capacitor charges
to store the excess energy. The situation is depicted in
Figure 26.
Figure 26. Output Voltage Ripple for a Constant Output Power
V
OUT
P
OUT
P
IN
Iac
Vac
As a consequence, the output voltage exhibits a ripple at
a frequency of either 100 Hz (for 50 Hz mains such as in
Europe) or 120 Hz (for 60 Hz mains in the USA). This
ripple must not be taken into account by the regulation loop
because the error amplifiers output voltage must be kept
constant over a given ac line cycle for a proper shaping of
the line current. Due to this constraint, the regulation
bandwidth is typically set below 20 Hz. For a simple type 1
compensation network, only a capacitor is placed between
FB and Control (see Figure 1). In this configuration, the
capacitor necessary to attenuate the bulk voltage ripple is
given by:
C
COMP
+
10
G
20
4 @ p f
line
@ R
OUT1
(eq. 4)
where G is the attenuation level in dB (commonly 60 dB)
ON TIME SEQUENCE
Since the NCP1607 is designed to control a CRM boost
converter,   its   switching   pattern   must   accommodate
constant on times and variable off times. The Controller
generates the on time via an external capacitor connected
to pin 3 (Ct). A current source charges this capacitor to a
level determined by the Control pin voltage. Specifically,
Ct is charged to V
CONTROL
 minus the V
EAL
 offset (2.1 V
typical). Once this level is exceeded, the drive is turned off
(Figure 27).
Figure 27. On Time Generation
Control
Ct
+

PWM
+
DRV
I
CHARGE
t
on
V
EAL
V
CONTROL
  V
EAL
t
on
V
Ct
V
Ct(off)
V
DD
DRV
V
CONTROL
Since V
CONTROL
 varies with the RMS line level and
output load, this naturally satisfies equation 1. And if the
values of compensation components are sufficient to filter
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