參數(shù)資料
型號: NCP1381DR2G
廠商: ON SEMICONDUCTOR
元件分類: 穩(wěn)壓器
英文描述: Low−Standby High Performance PWM Controller
中文描述: 1 A SWITCHING CONTROLLER, 125 kHz SWITCHING FREQ-MAX, PDSO14
封裝: LEAD FREE, SOIC-14
文件頁數(shù): 11/26頁
文件大小: 559K
代理商: NCP1381DR2G
NCP1381
http://onsemi.com
11
Figure 9.
I
nternal QR Architecture
+
V
DD
+
Fault
+
+
V
DD
+
+
V
DD
2
+
+
Demag
DRV
45 mV
Prioritary
Reset
R
S
Q
Q
CLK
D
V
DD
One
Shot
DRV
R
S
Q
Q
CLK
D
DRV
Skip
Reset Reset
I
3 s
Blanking
1.00
1.00
3.00
5.00
7.00
Figure 10. Core Reset Detection is Done Through the
Monitoring of a Dedicated Auxiliary Winding
0 V
45 mV
Possible
Restart
D
Skipping Cycle Mode
The NCP1381 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin 6 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the socalled skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 11) and
follows the following formula:
1
2
with
L
P
= Primary Inductance
F
sw
= Switching Frequency Within the Burst
I
P
= Peak Current at which Skip Cycle Occurs
D
burst
= Burst Width/Burst Recurrence
LP
IP
2
Fsw
Dburst
(eq. 1)
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