參數(shù)資料
型號(hào): NCP1381DR2G
廠商: ON SEMICONDUCTOR
元件分類: 穩(wěn)壓器
英文描述: Low−Standby High Performance PWM Controller
中文描述: 1 A SWITCHING CONTROLLER, 125 kHz SWITCHING FREQ-MAX, PDSO14
封裝: LEAD FREE, SOIC-14
文件頁數(shù): 16/26頁
文件大?。?/td> 559K
代理商: NCP1381DR2G
NCP1381
http://onsemi.com
16
100
100
300
500
700
Figure 22. Plateau Sensing Overvoltage Protection
Figure 23. Typical Sensed Waveforms
TIME ( S)
I
P
T
samp
58.5
62.5
66.5
70.4
74.4
+
V
latchdem
Latch
Input
To Demag
Comp.
DRV
Demag
1 Shot
Timer
+
External Latchoff
By lifting up Pin 5 above V
latch
(3.5 V typical), the circuit
is permanently latched. That is to say, Pin 9 goes low, the
GTS pin no longer supplies the PFC and the V
CC
is clamped
to 6 V. The latch reset occurs when V
CC
falls below 4 V, e.g.
when the user unplugs the converter from the mains.
Figure 24 shows several options on how to connect a PNP
to implement an OVP or Overtemperature Protection
(OTP).
Figure 24. Wiring a PNP Transistor on the Skip Cycle Input Pin will Latch the Circuit.
+
V
latch
Skip
NTC
Latch
V
max
< 5 V!
V
ref
OVP
V
ref
+
Skip
+
Latch
OVP
Skip
V
latch
+
Keep in mind that the 5 V maximum limit on all low
voltage pins implies some precaution when triggering the
latch voltage. The cheapest option is obtained when wiring
a simple zener diode in series with the monitored line. Care
must be taken to limit the excursion of the skip pin before
fully latching the controller.
GoToStandby detection
The PFC frontend stage delivers an elevated voltage to
the Flyback converter and keeps the mains power factor
close to unity. However, in standby, this PFC stage is no
longer needed and must be turned off to save watts and thus
reduce the noload standby power. To detect when the
converter enters standby, the controller observes the voltage
available on Pin 1: typically, a portion of the feedback
voltage will be used. In higher power conditions, this level
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