參數(shù)資料
型號(hào)： NCP1381
廠商： ON SEMICONDUCTOR
英文描述： Low−Standby High Performance PWM Controller
文件頁(yè)數(shù)： 17/26頁(yè)
文件大?。?/td> 559K
代理商： NCP1381
NCP1381
http://onsemi.com
17
is high, in low power conditions, this voltage is low.
Unfortunately, the situation complicates with QR converters
since the input voltage plays a significant role in the
feedback voltage evolution. A case can happen where the
converter is supplied by a 400 V rail and suddenly enters
standby: the PFC turns off and the bulk voltage goes low,
let’s say 120 VDC (V
in
= 85 VAC). At this time, the power
transfer changes, the propagation delay plays a smaller role
and the feedback voltage naturally goes up again. If a
sufficient hysteresis is not built, there are possibilities to see
hiccup on the PFC V
CC
, which is not a desirable feature.
Therefore, hysteresis is mandatory on top of the
GoToStandby (GTS) detection level. For this reason it is
possible to increase the hysteresis of the ADJ_GTS
comparator due to an internal 5 A current source that can
create an offset to the input signal if a series resistor is
inserted. The ADJ_GTS detection level is also adjustable by
tuning the portion of the external signal applied to Pin 1 (the
reference of the internal comparator is 250 mV).
Again, to check how we manage the feedback variations,
we can plot these variations without compensation for a
given power, and with the offset resistor connected to the CS
pin. In the first case, the FB voltage dependency on V
in
can
be expressed by:
FB(Vin) :
2
PO
N
(Vout
Vin
VF)
(Vout
Vin
VF)
N
Vin
LP
tP
(eq. 6)
RS
FBCS
Where FB
CS
is the ratio between the FB level and the current
setpoint. In our controller, this ratio is 4. If we now
incorporate our offset voltage generated by the R
offset
resistor and the input voltage, the compensated FB variation
expression becomes:
FBComp(Vin) :
2
PO
N
(Vout
Vin
VF)
(Vout
Vin
VF)
N
(eq. 7)
Vin
LP
FBCS
tP]
RS
Vin
gm
Roffset]
with the BO divider ratio (0.00414 in our example), gm
the transconductance slope of 80 S and R
offset
, the selected
offset resistor.
If now plot Equation 6 and Equation 7 for a 8 W output
power, we will obtain Figures 25 and 26:
Figure 25. Uncompensated FB Variations for
P
out
= 8 W
Figure 26. Compensated FB variations
P
out
= 8 W
V
in
, VOLTAGE (V)
F
(
0.35
0.3
0.25
0.2
0.15
0.1
100
150
200
250
300
350
400
V
in
, VOLTAGE (V)
F
C
100
150
200
250
300
350
400
0.75
0.7
0.65
0.6
0.55
0.5
0.45
As one can see on Figure 26, the FB level now falls down
when the PFC is shut off. It now goes in the right direction
(FB growing up with V
in
) and this plays in our favor to not
cross again the upper comparison level, as it could be the
case in Figure 25. However, we must check that the offset
programmed by R
offset
(147 mV in our example) multiplied
by 4, is still below our skip cycle level, otherwise the
converter will never enter skip at high line (the permanent
offset at high line will force a higher feedback):
0.147
4
588 mV
0.75 V
(eq. 8)
This is okay.
The drawback of Figure 26 is the higher forced level for
lower power outputs. In our example, a 90 W adapter, the
PFC will be shutdown at P
out
= 8 W, or a bit less than 10%
of the nominal power. If the designer needs to increase or
decrease this value, it can adjust the ADJ_GTS level, still
keeping in mind Equation 8 relationship.
To avoid a false tripping, the timer (90 ms with Pin 4
capacitor of 220 nF) will be started every time the GTS
signal goes high. If at the end of the 90 ms the GTS signal
is still high, the standby is confirmed and the SW switch
between Pins 11 and 10 opens. To the opposite, when the
output power is needed, there is no delay and the SW switch
turns on immediately. Figure 27 zooms on the internal
circuitry whereas Figure 28 shows typical signal evolutions:
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