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NCN6001
http://onsemi.com
33
Table of Contents
COMPACT SMART CARD INTERFACE IC
MAXIMUM RATINGS
DIGITAL PARAMETERS SECTION
POWER SUPPLY SECTION
SMART CARD INTERFACE SECTION
PROGRAMMING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
START UP DEFAULT CONDITIONS
CARD DETECTION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRD_VCC OPERATION
. . . . . . . . . . . . . . . . . . . . . . . . . .
POWER UP SEQUENCE
. . . . . . . . . . . . . . . . . . . . . . . . .
POWER DOWN SEQUENCE
DATA I/O LEVEL SHIFTER
GENERAL PURPOSE CRD_C4 and CRD_C8
INTERRUPT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI PORT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC/DC OPERATION
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMART CARD CLOCK DIVIDER
INPUT SHITTY TRIGGERS
SECURITY FEATURES
. . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD PROTECTION
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PRINTED CIRCUIT BOARD LAY OUT
TEST BOARD SCHEMATIC DIAGRAM
ABBREVIATIONS
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DIMENSIONS
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1
6
7
8
9
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11
14
14
14
14
16
17
18
19
20
22
26
28
28
28
28
29
34
35
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Figures Index
Figure 1. Typical Application
2
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Figure 2. Block Diagram
2
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Figure 3. Typical Start Up CRD_VCC Sequence
14
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Figure 4. CRD_VCC Typical Rise and Fall Time
15
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Figure 5. Start Up Sequence with ATR
15
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Figure 6. Typical Power Down Sequence
16
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Figure 7. Basic I/O Internal Circuit
17
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Figure 8. Typical I/O Rise and Fall Time
17
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Figure 9. Typical CRD_C4 Output Drive and Logic Control
18
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Figure 10. Basic Interrupt Function
19
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Figure 11. Basic SPI Timings and Protocol
20
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Figure 12. Chip Address Decoding Protocol and MISO
Sequence
20
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Figure 13. Basic Multi Command SPI Bytes
21
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Figure 14. Programming Sequence, Chip Address = $03
21
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Figure 15. MISO Read Out Sequences
22
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Figure 16. Basic DC/DC Converter
22
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Figure 17. Theoretical DC/DC Operating Waveforms
23
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Figure 18. Typical CRD_VCC Ripple Voltage
24
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Figure 19. CRD_VCC Efficiency as a Function of the Input
Supply Voltage
24
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Figure 20. CRD_VCC Efficiency as a Function of the Input
Supply Voltage
24
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Figure 21. Typical Inductor Current
25
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Figure 22. Output Current Limits
25
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Figure 23. Output Current Limit as a Function of the
Temperature
25
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Figure 24. Typical Clock Divider Synchronization
26
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Figure 25. Basic Clock Divider and Level Shifter
26
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Figure 26. Force CRD_CLK to Low
27
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Figure 27. Force CRD_CLK to Active Mode
27
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Figure 28. CRD_CLK Programming
27
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Figure 29. CRD_CLK Operating Low Speed (Top Trace),
Full Speed (Bottom Trace)
27
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Figure 30. Typical Schmitt Trigger Characteristic
28
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Figure 31. NCN6001 Engineering Test Board Schematic
Diagram
29
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Figure 32. NCN6001 Demo Board Printed Circuit Board
Layout
30
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Figure 33. Typical Multiple Parallel Interfaces
32
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Tables Index
DIGITAL PARAMETERS.
7
. . . . . . . . . . . . . . . . . . . . . . . . . . .
POWER SUPPLY.
8
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SMART CARD INTERFACE.
9
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Table 1. WRT_REG Bits Definitions
11
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Table 2. WRT_REG Bits Definitions and Functions
12
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Table 3. MOSI and MISO Bits Identifications and Functions
13
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Table 4. Start Up Default Conditions
14
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Table 5. CRD_VCC Output Voltage Range
14
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Table 6. I/O Pull Up Resistor True Table
17
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Table 7. Interrupt Reset Logic
19
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Table 8. Interrupt Reset Logic Operation
19
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Table 9. Ceramic/Electrolytic Capacitors Comparison
24
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Table 10. Output Clock Rise and Fall Time Selection
27
. .
Table 11. Demo Board Bill of Material
31
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