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參數(shù)資料
| 型號(hào)： | NB6L611MNR2G |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER 1:2 4GHZ 16-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ECLinPS MAX™ |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，LVCMOS，LVDS，LVPECL，LVTTL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 4GHz |
| 電源電壓： | 2.375 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN（3x3） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | NB6L611MNR2GOSCT |
Semiconductor Components Industries, LLC, 2009
August, 2009 Rev. 4
1
Publication Order Number:
NB6L611/D
NB6L611
2.5V / 3.3V 1:2 Differential
LVPECL Clock / Data Fanout
Buffer
MultiLevel Inputs with Internal Termination
Description
The NB6L611 is a differential 1:2 clock or data fanout buffer. The
differential inputs incorporate internal 50
W termination resistors that
are accessed through the VTD pins and will accept LVPECL, CML,
LVDS, LVCMOS or LVTTL logic levels.
The VREFAC reference output can be used to rebias
capacitorcoupled differential or singleended input signals. When
used, decouple VREFAC with a 0.01 mF capacitor and limit current
sourcing or sinking to 0.5 mA. When used, decouple VREFAC with a
0.01
mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, VREFAC output should be left open.
The device is housed in a small 3x3 mm 16 pin QFN package.
The NB6L611 is a member of the ECLinPS MAX
family of high
performance clock and data management products.
Features
Input Clock Frequency > 4.0 GHz
280 ps Typical Propagation Delay
100 ps Typical Rise and Fall Times
0.5 ps maximum RMS Clock Jitter
Differential LVPECL Outputs, 780 mV Amplitude, typical
LVPECL Operating Range: VCC = 2.375 V to 3.63 V with VEE = 0 V
NECL Operating Range: VCC = 0 V with VEE = 2.375 V to 3.63 V
Internal Input Termination Resistors, 50 W
VREFAC Reference Output Voltage
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
MARKING
DIAGRAM*
http://onsemi.com
QFN16
MN SUFFIX
CASE 485G
NB6L
611
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
(Note: Microdot may be in either location)
16
1
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
Figure 1. Simplified Logic Diagram
Q0
Q1
D
VTD
VREFAC
1
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