參數(shù)資料
型號(hào): NB6N11SMNR2G
廠商: ON Semiconductor
文件頁(yè)數(shù): 1/10頁(yè)
文件大小: 0K
描述: IC CLK BUFFER TRANSLA 1:2 16-QFN
標(biāo)準(zhǔn)包裝: 3,000
系列: AnyLevel™ ECLinPS MAX™
類型: 扇出緩沖器(分配),變換器
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
輸入: CML,LVCMOS,LVDS,LVPECL,LVTTL
輸出: LVDS
頻率 - 最大: 2GHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2011
June, 2011 Rev. 6
1
Publication Order Number:
NB6N11S/D
NB6N11S
3.3 V 1:2 AnyLevelE Input
to LVDS Fanout Buffer /
Translator
Description
The NB6N11S is a differential 1:2 Clock or Data Receiver and will
accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL,
or LVDS. These signals will be translated to LVDS and two identical
copies of Clock or Data will be distributed, operating up to 2.0 GHz or
2.5 Gb/s, respectively. As such, the NB6N11S is ideal for SONET,
GigE, Fiber Channel, Backplane and other Clock or Data distribution
applications.
The NB6N11S has a wide input common mode range from
GND + 50 mV to VCC 50 mV. Combined with the 50 W internal
termination resistors at the inputs, the NB6N11S is ideal for
translating a variety of differential or singleended Clock or Data
signals to 350 mV typical LVDS output levels.
The NB6N11S is functionally equivalent to the EP11, LVEP11,
SG11 or 7L11M devices and is offered in a small, 3 mm X 3 mm,
16QFN package. Application notes, models, and support
documentation are available at www.onsemi.com.
The NB6N11S is a member of the ECLinPS MAX
family of high
performance products.
Features
Maximum Input Clock Frequency > 2.0 GHz
Maximum Input Data Rate > 2.5 Gb/s
1 ps Maximum of RMS Clock Jitter
Typically 10 ps of Data Dependent Jitter
380 ps Typical Propagation Delay
120 ps Typical Rise and Fall Times
Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and
SG Devices
These are PbFree Devices
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 2231 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
VOL
TAGE
(130
mV/div)
Device DDJ = 10 ps
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN16
MN SUFFIX
CASE 485G
http://onsemi.com
1
Q0
Q1
D
VTD
Figure 1. Logic Diagram
(Note: Microdot may be in either location)
16
NB6N
11S
ALYW G
G
1
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
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