參數(shù)資料
型號(hào): N74F269D,602
廠商: NXP Semiconductors
文件頁數(shù): 2/19頁
文件大?。?/td> 0K
描述: IC COUNTER 8BIT BINARY 24SOIC
產(chǎn)品培訓(xùn)模塊: Logic Packages
標(biāo)準(zhǔn)包裝: 30
系列: 74F
邏輯類型: 二進(jìn)制計(jì)數(shù)器
方向: 上,下
元件數(shù): 1
每個(gè)元件的位元數(shù): 8
計(jì)數(shù)速率: 115MHz
觸發(fā)器類型: 正邊沿
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SO
包裝: 管件
其它名稱: 933784250602
N74F269D
N74F269D-ND
74F269
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 14 December 2011
10 of 19
NXP Semiconductors
74F269
8-bit bidirectional binary counter
11. Waveforms
tsu(H)
set-up time HIGH
Dn to CP; see Figure 10
3.5
-
2.5
-
ns
PE to CP; see Figure 10
5.5
-
5.5
-
ns
CEP or CET to CP; see Figure 11
6.0
-
5.0
-
ns
U/D to CP; see Figure 12
8.0
-
6.5
-
ns
tsu(L)
set-up time LOW
Dn to CP; see Figure 10
3.5
-
2.5
-
ns
PE to CP; see Figure 10
6.5
-
6.5
-
ns
CEP or CET to CP; see Figure 11
8.0
-
6.5
-
ns
U/D to CP; see Figure 12
6.5
-
6.5
-
ns
th(H)
hold time HIGH
Dn to CP; see Figure 10
1.0
-
0
-
ns
PE to CP; see Figure 10
0-
-
0
-
ns
CEP or CET to CP; see Figure 11
0-
-
0
-
ns
U/D to CP; see Figure 12
0-
-
0
-
ns
th(L)
hold time LOW
Dn to CP; see Figure 10
1.0
-
1.0
-
ns
PE to CP; see Figure 10
0-
-
0
-
ns
CEP or CET to CP; see Figure 11
0-
-
0
-
ns
U/D to CP; see Figure 12
0-
-
0
-
ns
tWH
pulse width HIGH
CP; see Figure 7
4.0
-
4.0
-
ns
tWL
pulse width LOW
CP; see Figure 7
4.5
-
5.0
-
ns
fmax
maximum
frequency
100
115
-
85
-
MHz
Table 7.
Dynamic characteristics …continued
GND = 0 V; for test circuit, see Figure 13.
Symbol Parameter
Conditions
25
C; V
CC = 5.0 V
0
C to 70 C;
VCC =5.0 V 0.5 V
Unit
Min
Typ
Max
Min
Max
Measurement points are given in Table 8.
VM =1.5 V
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 7.
Clock (CP) to outputs (Qn, TC) propagation delay, the clock pulse width
001aal292
CP input
Qn, TC output
tPHL
tPLH
tWH
tWL
1/fmax
VM
VOH
VI
GND
VOL
VM
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