參數(shù)資料
型號： N74F269D,602
廠商： NXP Semiconductors
文件頁數(shù)： 19/19頁
文件大?。?/td> 0K
描述： IC COUNTER 8BIT BINARY 24SOIC
產(chǎn)品培訓(xùn)模塊： Logic Packages
標(biāo)準(zhǔn)包裝： 30
系列： 74F
邏輯類型： 二進(jìn)制計數(shù)器
方向： 上，下
元件數(shù)： 1
每個元件的位元數(shù)： 8
計數(shù)速率： 115MHz
觸發(fā)器類型： 正邊沿
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SO
包裝： 管件
其它名稱： 933784250602
N74F269D
N74F269D-ND
74F269
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 14 December 2011
9 of 19
NXP Semiconductors
74F269
8-bit bidirectional binary counter
9.
Static characteristics
[1]
All typical values are measured at VCC =5V.
[2]
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
10. Dynamic characteristics
Table 6.
Static characteristics
Symbol Parameter
Conditions
25
C
40 C to +85 C Unit
Min
Max
Min
Max
VIK
input clamping voltage
VCC = 4.5 V; IIK = 18 mA
1.2 0.73
-
1.2
-
V
VOH
HIGH-level output
voltage
VCC = 4.5 V; VI = VIL or VIH
VCC = 10 %; IOH = 1mA
-
2.5
-
V
VCC = 5%; IOH = 1 mA
-
3.4
-
2.7
-
V
VOL
LOW-level output
voltage
VCC = 4.5 V; IOL =20mA;
VI =VIL or VIH
VCC = 10 %
-
0.30
-
0.50
V
VCC = 5%
-
0.30
-
0.50
V
II
input leakage current
VCC = 5.5 V; VI =7.0 V
-
100
A
IIH
HIGH-level input current VCC = 5.5 V; VI =2.7 V
-
20
A
IIL
LOW-level input current
VCC = 5.5 V; VI = 0.5 V
-
0.6
mA
IO
output current
VCC = 5.5 V
--
-
60
150
mA
ICC
supply current
PE = CET =CEP =U/D = GND;
VCC = 5.5 V; CP = rising edge
Dn: VI =4.5 V
-
93
-
120
mA
Dn: VI =GND
-
98
-
125
mA
Table 7.
Dynamic characteristics
GND = 0 V; for test circuit, see Figure 13.
Symbol Parameter
Conditions
25
C; V
CC = 5.0 V
0
C to 70 C;
VCC =5.0 V 0.5 V
Unit
Min
Typ
Max
Min
Max
tPLH
LOW to HIGH
propagation delay
CP to Qn; load; PE = LOW; see Figure 7
3.0
6.0
8.5
3.0
9.0
ns
CP to Qn; count; PE = HIGH; see Figure 7
3.0
6.0
9.0
3.0
10.0
ns
CP to TC; see Figure 7
4.5
6.5
9.5
4.0
10.5
ns
CET to TC; see Figure 8
3.5
6.0
9.0
3.0
10.0
ns
U/D to TC; see Figure 9
4.5
7.0
9.0
4.0
10.0
ns
tPHL
HIGH to LOW
propagation delay
CP to Qn; load; PE = LOW; see Figure 7
4.0
6.5
8.5
4.0
9.0
ns
CP to Qn; count; PE = HIGH; see Figure 7
4.5
7.0
10.0
4.0
10.5
ns
CP to TC; see Figure 7
5.0
6.5
9.5
5.0
10.0
ns
CET to TC; see Figure 8
3.0
6.5
9.0
3.0
10.0
ns
U/D to TC; see Figure 9
4.5
7.0
9.5
4.0
10.0
ns
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