
1
P/N:PM0484
REV. 1.6, MAY. 29, 2000
1. FEATURES
A single chip solution integrates 100/10 Base-T fast
Ethernet MAC, PHY and PMD
Fully comply to IEEE 802.3u specification
Operates over 100 meters of STP and category 5 UTP
cable
Fully comply to PCI spec. 2.1 up to 33MHz
Support full and half duplex operations in both
100Base-TX and 10 Base-T mode
Magic Packet TM mode to support Remote-Wake-Up
100/10 Base-T NWAY auto negotiation function
Large on-chip FIFOs for both transmit and receive
operations without external local memory
Bus master architecture with linked host buffers deliv-
ers the most optoimized performance
32-bit bus master DMA channel provides ultra low
CPU utilization
Proprietary Adaptive Network Throughput Control
(ANTC) technology to optimize data integrity and
throughput
Support up to 64K bytes boot ROM interface
Three levels of loopback diagnositic capability
Support a variety of flexible address filtering modes
with 16 CAM address and 512 bits hash
MicroWire interface to EEPROM for customer's IDs
and configuration data
Single +5V power supply, standard CMOS technol-
ogy, 128-pin PQFP package
( Magic Packet Technology is a trademark of Advanced
Micro Device Corp. )
2. GENERAL DESCRIPTIONS
The MX98715EC controller is an IEEE802.3u compliant
single chip 32-bit full duplex, 10/100Mbps highly inte-
grated Fast Ethernet combo solution, designed to ad-
dress high performance local area networking (LAN)
system application requirements.
MX98715EC's PCI bus master architecture delivers the
utilimized performance for future high speed and pow-
erful processor technologies. In other words, the
MX98715EC not only keeps CPU utilization low while
maximizing data throughput, but it also optimizes the
PCI bandwidth providing the highest PCI bandwidth utili-
zation. To further reduce maintenance costs the
MX98715EC uses drivers that are backward compatible
with the original MXIC MX98713 series controllers.
The MX98715EC contains a PCI local bus glueless in-
terface, a Direct Memory Access (DMA) buffer manage-
ment unit, an IEEE802.3u-compliant Media Access Con-
troller (MAC), large Transmit and Receive FIFOs, and
an on-chip 10 Base-T and 100 Base-TX transceiver sim-
plifying system design and improving high speed signal
quality. Full-duplex operation are supported in both 10
Base-T and 100 Base-TX modes that increases the
controller's operating bandwidth up to 200Mbps.
Equipped with intelligent IEEE802.3u-compliant auto-ne-
gotiation, the MX98715EC-based adapter allows a single
RJ-45 connector to link with the other IEEE802.3u-com-
pliant device without re-configuration.
In MX98715EC, an innovative and proprietary design
"Adaptive Network Throughput Control" (ANTC) is built-
in to configure itself automatically by MXIC's driver based
on the PCI burst throughput of different PCs. With this
proprietary design, MX98715EC can always optimize its
operating bandwidth, network data integrity and through-
put for different PCs.
MXIC MX98715EC features Remote-Wake-Up capabil-
ity that enables a wide range of wake-up capabilities,
including the ability to customize the content of speci-
fied packet which PC should to respend to, even when it
is in a low-power state. PCs and workstations could
take advantage of these capabilities of being waked up
and serviced simultaneiously over the network by remote
server or workstation. It helps organizations reduce their
maintenance cost of high-performance business PCs.
With its on-chip support for both little and big endian
byte alignment, MX98715EC can also address non-PC
applications.
MX98715EC
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
PRELIMINARY