- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359265 > MX805LH RF/Baseband Circuit PDF資料下載
參數(shù)資料
| 型號(hào)： | MX805LH |
| 英文描述： | RF/Baseband Circuit |
| 中文描述： | 射頻/基帶電路 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 532K |
| 代理商： | MX805LH |
Sub-Audio Signaling Processor
5.2.3
Read Status Register –A/C 71
H
(79
H
) followed by 1 byte of Rely Data.
The Status Register indicates the operational condition of the MX805A. Bits 0 to 5 are set individually to
indicate specific actions within the device. When a Status bit is set to a logic “1”, and Interrupt Request (IRQ)
output is generated. A read of the Status Register will reset the Interrupt and ascertain the state of this
register. Table 7 shows the conditions indicated by the Status bits.
Setting
Set By
Logic
Received First
7, 6
Not Used
5
NRZ data transmission complete.
No new data is loaded.
Page 13 of 24
MX805A
2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
All trademarks and service marks are held by their respective companies.
Doc. # 20480116.005
Cleared By
Not Used
1. Write to NRZ Data Reg., or
2. General Reset, or
3. NRZ Encoder Powersave
1. Write to NRZ TX Data Reg., or
2. General Rest, or
3. NRZ TX Powersave
1. Read NRZ RX Data Reg., or
2. General Reset, or
3. NRZ Decoder powersave
1. Read NRZ RX Data Reg., or
2. General Reset, or
3. NRZ Decoder powersave
1. Read Status Register, or
2. General Rest, or
3. CTCSS Decoder Powersave
1. Read Status Register, or
2. General Reset, or
3. CTCSS Decoder Powersave
Logic
0
0
MSB
0
1
4
NRZ TX Data Buffer ready for next
data byte.
1
0
3
New NRZ RX data received before
last byte was read.
1
0
2
1 byte of NRZ data received
1
0
1
NoTone timer period expired
1
0
0
RX Tone Measurement Complete
1
0
Table 7: Status Register
5.2.4
5.2.4.1
The input sub-audio signal (f
CTCSS
IN
) is filtered, doubled and measured in the Frequency Counter over the
“measurement period” (122.64ms) (4.0MHz Xtal).
The measuring function counts the number of complete input cycles occurring within the measurement period
and the number of measuring-clock cycles necessary to make up one period.
When the measurement period of a successful decode is complete, the RX Tone Measurement bit in the
Status Register and the Interrupt bit are set.
The CTCSS RX Frequency Register will now indicated the sub-audio signal frequency (f
CTCSS
IN
) in the form
of 2 data bytes (1 and 0) as illustrated in Figure 6.
Read CTCSS RX Frequency Register –A/C 72
H
(7A
H
) followed by 2 bytes of Reply Data
Measurement of CTCSS RX Frequency (f
CTCSS
IN
)
Complete
Input
Cycle
Complete
Input
Cycle
Complete
Input
Cycle
Complete
Input
Cycle
Complete
Input
Cycle
Measuring
Clock
Cycles
Measurement Period
N
R
FILTERED AND DOUBLED SUB-AUDIO INPUT SIGNAL
2 x f
CTCSS IN
Figure 5: Measurement of a CTCSS RX Frequency
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MX806ADW | Audio Processor |
| MX806ALH | Audio Processor |
| MX806J | Audio Processor |
| MX806LH | Audio Processor |
| MX809LH | MODEM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MX806A | 制造商:CMLMICRO 制造商全稱:CML Microcircuits 功能描述:Audio Processor |
| MX806ADW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio Processor |
| MX806AJ | 制造商:CMLMICRO 制造商全稱:CML Microcircuits 功能描述:Audio Processor |
| MX806ALH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio Processor |
| MX806J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Audio Processor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。