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參數(shù)資料
| 型號： | MX29LV040TI-90 |
| 廠商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分類： | DRAM |
| 英文描述： | 10A 100V Schottky Rectifier; Package: TO-220AC 2 LEAD; No of Pins: 2; Container: Rail; Qty per Container: 50 |
| 中文描述： | 512K X 8 FLASH 3V PROM, 90 ns, PDSO32 |
| 封裝： | 8 X 20 MM, PLASTIC, MO-142, TSOP1-32 |
| 文件頁數(shù)： | 9/51頁 |
| 文件大?。?/td> | 713K |
| 代理商： | MX29LV040TI-90 |
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9
P/N:PM0722
MX29LV040
REV. 0.7, JUL. 12, 2001
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage(VID). However, multiplexing high voltage
onto address lines is not generally desired system de-
sign practice.
The MX29LV040 contains a Silicon-ID-Read operation
to supple traditional PROM programming methodology.
The operation is initiated by writing the read silicon ID
command sequence into the command register. Fol-
lowing the command write, a read cycle with A1=VIL,
A0=VIL retrieves the manufacturer code of C2H. A read
cycle with A1=VIL, A0=VIH returns the device code of
4FH for MX29LV040.
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cy-
cles are then followed by the chip erase command 10H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verification command is required).
If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 6), indicating the erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE or CE pulse, whichever happens first in the
command sequence and terminates when the data on
Q7 is "1" and the data on Q6 stops toggling for two con-
secutive read cycles, at which time the device returns
to the Read mode.
Pins
A0
A1
Q7
Q6
Q5
Q4
Q3
Q2
Q1 Q0
Code(Hex)
Manufacture code
VIL
VIL
X
1
0
0
0
0
1
0
C2H
Device code
VIH
VIL
0
1
0
0
1
1
1
1
4FH
Sector Protection Verification
VIL
VIH
0
0
0
0
0
0
0
0
00H (Unprotected)
TABLE 5. EXPANDED SILICON ID CODE
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相關(guān)代理商/技術(shù)參數(shù) |
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| MX29LV160BBTC-90 | 制造商:MX-COM Inc 功能描述:1M X 16 FLASH 3V PROM, 90 ns, PDSO48 |
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| MX29LV160DBTI-70G | 功能描述:IC FLASH PAR 3V 16MB 70NS 48TSOP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:MX29LV 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:4G（256M x 16） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP I 包裝:Digi-Reel® 其它名稱:557-1461-6 |
| MX29LV160DBTI-70GTR | 制造商:Macronix International Co Ltd 功能描述: |
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