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參數(shù)資料
| 型號(hào)： | MUAA8K80M-20B388C |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 395K |
| 代理商： | MUAA8K80M-20B388C |
MUAA Routing CoProcessor (RCP) Family
Operational Characteristics
8
Rev. 3
OPERATIONAL CHARACTERISTICS
Loading and Unloading
In order to keep data alignment simple, the number of
words to be loaded and unloaded for each operation is kept
consistent for each CAM/RAM partition configuration and
the width of the port.
Tables 2 and 3 show the cycle sequence and CAM/RAM
bit mappings for 32- and 16-bit bus modes. The bus may
be selected for each port independently. Table 4 shows
whether CAM, RAM or both types of segments are used
on input or output cycles for each operation.
Loads always start right aligned from the least significant
word, CAM partition first, followed by RAM if necessary.
Most instructions do not require the entire 80 bits to be
loaded.
CAM data is required as an input for all operations except
READ LQUEUE and READ AQUEUE. The use of RAM
data is optional (i.e., it is not necessary to perform all
RAM cycles when inputting data). However, the user must
be aware that INSERT and LEARN operations will
over-write RAM data. Therefore, the application should
remain consistent in the number of RAM bits used for
these operations.
All CAM and RAM segment writes except the last use the
LOAD instruction. The last segment of data uses the
instruction for the desired operation.
Depending on the operation, unloads either start from the
right aligned, least significant word of CAM followed by
the right aligned, least significant word of RAM or just
from the right aligned, least significant word of RAM. For
instance, a QUEUE read returns CAM then RAM,
whereas a search just returns RAM. Where the
CAM/RAM partition does not lie on a port width
boundary the last word of the read may contain undefined
data in the most significant bits. The number of unload
cycles actually completed is optional.
The DOUT register stores the results of operations from
the asynchronous processor port. Search results are
obtained by repeated reads of DOUT until all RAM data is
read. When performed from the processor port, READ
LQUEUE and READ AQUEUE return the first segment
of CAM data on the cycle that requests the operation;
additional CAM and RAM segments are obtained by
repeated reads of the DOUT register.
Loading is flow controlled on the synchronous DIN port
with the DINREADY signal, which is HIGH when data is
accepted by the DIN port. On the Processor port the
PROCREADY signal is HIGH when the current write
cycle may complete.
Ground
GND
Device ground.
N/A
AF1, AF2, AF24, AF25, AF26
AE1, AE2, AE24, AE25, AE26
AD1–AD6, AD9– AD12, AD15,
AD16, AD21, AD24, AD25,
AD26, AC3–AC6, AC9–AC12
AC15, AC16, AC21,
AC24–AC26, AB4, AB23–AB26,
AA4, AA23, AA24, V3, V4, V23,
V24, U4, U23, U24, T4,
T11–T16, T23, T24, R11, R16,
R23, R24, P11, P13, P14, P16,
N4, N11, N13, N14, N16, M11,
M16, M23, M24, L11–L16, L23,
L24, K23, K24 J23, J24, F23,
F24, E23–E26, D2–D5, D8, D9,
D12–D14, D17–D19, D22–D26,
C1–C5, C8, C9, C12–C14,
C17–C19, C22– C26, B1–B5,
B22–B26, A1–A5, A22–A26
Table 1: Ball Descriptions (continued)
Functional
Group
Ball Name(s)
Function
Type
PBGA Ball(s)
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