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參數(shù)資料
| 型號(hào)： | MTV212MN64 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded Monitor Controller Flash Type with ISP |
| 中文描述： | 8051嵌入式控制器的閃存供應(yīng)商監(jiān)視器類型 |
| 文件頁(yè)數(shù)： | 8/23頁(yè) |
| 文件大?。?/td> | 167K |
| 代理商： | MTV212MN64 |
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MYSON
TECHNOLOGY
MTV212A32
(Rev. 1.2)
Revision 1.2 - 8 - 2000/07/04
= 4
= 5
→
Select AUXRAM bank 0.
→
Select AUXRAM bank 1.
4. Extra I/O
The extra I/O is a group of I/O pins located in XFR area. Port4 is output mode only. Port5 can be used as
both output and input, because Port5's pin is open drain type, user must write Port5's corresponding bit to
"1" in input mode.
Reg name
PORT4
PORT5
addr
38h (w)
39h (r/w)
bit7
bit6
bit5
bit4
bit3
bit2
P42
P52
bit1
P41
P51
bit0
P40
P50
P56
P55
P54
P53
PORT4
(w) :
Port 4 data output value.
PORT5
(r/w) :
Port 5 data input/output value.
5. PWM DAC
Each PWM DAC converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of
PWM clk is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253
or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high
output. If DIV253=0, the output will pulse low at least once even if the DAC register's content is FFH. Writing
00H to DAC register generates stable low output.
Reg name
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
addr
20h (r/w)
21h (r/w)
22h (r/w)
23h (r/w)
24h (r/w)
25h (r/w)
26h (r/w)
27h (r/w)
28h (r/w)
29h (r/w)
2Ah (r/w)
2Bh (r/w)
2Ch (r/w)
2Dh (r/w)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Pulse width of PWM DAC 0
Pulse width of PWM DAC 1
Pulse width of PWM DAC 2
Pulse width of PWM DAC 3
Pulse width of PWM DAC 4
Pulse width of PWM DAC 5
Pulse width of PWM DAC 6
Pulse width of PWM DAC 7
Pulse width of PWM DAC 8
Pulse width of PWM DAC 9
Pulse width of PWM DAC 10
Pulse width of PWM DAC 11
Pulse width of PWM DAC 12
Pulse width of PWM DAC 13
DA0-13
(r/w) :
* All of PWM DAC converters are centered with value 80h after power on.
The output pulse width control for DA0-13.
6. H/V SYNC Processing
The H/V SYNC processing block performs the functions of composite signal separation/insertion, SYNC
inputs presence check, frequency counting, polarity detection and control, as well as the protection of
VBLANK output while VSYNC speed up in high DDC communication clock rate. The present and frequency
function block treat any pulse shorter than one OSC period as noise.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MTV212MV64I | 制造商:Myson Century Inc 功能描述:IC, 8051 EMBEDDED MONITOR CONTROLLER FLASH TYPE WITH ISP, PLCC44 |
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