參數(shù)資料
型號(hào)： MTV212MN64
廠商： Electronic Theatre Controls, Inc.
英文描述： 8051 Embedded Monitor Controller Flash Type with ISP
中文描述： 8051嵌入式控制器的閃存供應(yīng)商監(jiān)視器類(lèi)型
文件頁(yè)數(shù)： 15/23頁(yè)
文件大?。?/td> 167K
代理商： MTV212MN64
MYSON
TECHNOLOGY
MTV212A32
(Rev. 1.2)
Revision 1.2 - 15 - 2000/07/04
7. DDC & IIC Interface
7.1 DDC1 Mode
The MTV212A32 enters DDC1 mode after Reset. In this mode, VSYNC is used as data clock. The HSCL pin
should remain at high. The data output to the HSDA pin is taken from a shift register in MTV212A32. The
shift register fetch data byte from the DDC1 data buffer (DBUF) then send it in 9 bits packet formats which
includes a null bit (=1) as packet separator. The DBUF set the DbufI interrupt flag when the shift register
read out the data byte from DBUF. Software needs to write EDID data to DBUF as soon as the DbufI is set.
The DbufI interrupt is automatically cleared when Software writes a new data byte to DBUF. The DbufI
interrupt can be mask or enable by EDbufI control bit.
7.2 DDC2B Mode
The MTV212A32 switches to DDC2B mode when it detects a high to low transition on the HSCL pin. Once
MTV212A32 enters DDC2B mode, S/W can set IICpass control bit to allow HOST access EEPROM directly.
Under such condition, the HSDA and HSCL are directly bypassed to ISDA and ISCL pins. The other way to
perform DDC2 function is to clear IICpass and config the Slave A IIC block to act as EEPROM behavior. The
Slave A block's slave address can be chosen by S/W as 5-bits, 6-bits or 7-bits. For example, if S/W choose
5-bits slave address as 10100b, the slave IIC block A will respond to slave address 10100xxb and save the 2
LSB "xx" in XFR. This feature enables MTV212A32 to meet PC99 requirement.
The MTV212A32 will return to DDC1 mode if HSCL is kept high for 128 VSYNC clock period. However, it will
lock in DDC2B mode if a valid IIC address (1010xxxb) has been detected on HSCL/HSDA bus. The DDC2
flag reflects the current DDC status, S/W may clear it by writing a "0" to it.
7.3 Slave Mode IIC function Block
The slave mode IIC block is connected to HSDA and HSCL pins. This block can receive/transmit data using
IIC protocol. There are 2 slave addresses MTV212A32 can respond to. S/W may write the
SLVAADR/SLVBADR register to determine the slave addresses. The SlaveA address can be configured to
5-bits, 6-bits or 7-bits by S/W setting the SlvAbs1 and SlvAbs0 control bits.
In receive mode, the block first detects IIC slave address match condition then issues a SlvAMI/SlvBMI
interrupt. If the matched address is slave A, MTV212A32 will save the matched address's 2 LSB bits to
SlvAlsb1 and SlvAlsb0 register. The data from HSDA is shifted into shift register then written to
RCABUF/RCBBUF register when a data byte is received. The first byte loaded is word address (slave
address is dropped). This block also generates a RCAI/RCBI (receive buffer full interrupt) every time when
the RCABUF/RCBBUF is loaded. If S/W can't read out the RCABUF/RCBBUF in time, the next byte in shift
register will not be written to RCABUF/RCBBUF and the slave block return NACK to the master. This feature
guarantees the data integrity of communication. The WadrA/WadrB flag can tell S/W that if the data in
RCABUF/RCBBUF is a word address.
In transmit mode, the block first detects IIC slave address match condition then issues a SlvAMI/SlvBMI
interrupt. In the mean time, the SlvAlsb1/SlvAlsb0 is also updated if the matched address is slave A, and the
data pre-stored in the TXABUF/TXBBUF is loaded into shift register, result in TXABUF/TXBBUF empty and
generates a TXAI/TXBI (transmit buffer empty interrupt). S/W should write the TXABUF/TXBBUF a new byte
for next transfer before shift register empty. Fail to do this will cause data corrupt. The TXAI/TXBI occurs
every time when shift register reads out the data from TXABUF/TXBBUF.
The SlvAMI/SlvBMI is cleared by writing "0" to corresponding bit in INTFLG register. The RCAI/RCBI is
cleared by reading RCABUF/RCBBUF. The TXAI/TXBI is cleared by writing TXABUF/TXBBUF. If the control
bit ENSCL is set, the block will hold HSCL low until the RCAI/RCBI/TXAI/TXBI is cleared.
*Please see the attachments about "Slave IIC Block Timing".
7.4 Master Mode IIC Function Block
The master mode IIC block can be connected to the ISDA /ISCL pins or the HSDA/HSCL pins, select by
Msel control bit. Its speed can be selected to 50KHz-400KHz by S/W setting the MIICF1/MIICF0 control bit.
The software program can access the external IIC device through this interface. Since the EDID/VDIF data
and the display information share the common EEPROM, precaution must be taken to avoid bus conflicting
while Msel=0. In DDC1 mode or IICpass=0, the ISCL/ISDA is controlled by MTV212A32 only. In DDC2 mode
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