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| 型號： | MTV212MN64 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded Monitor Controller Flash Type with ISP |
| 中文描述： | 8051嵌入式控制器的閃存供應(yīng)商監(jiān)視器類型 |
| 文件頁數(shù)： | 16/23頁 |
| 文件大小： | 167K |
| 代理商： | MTV212MN64 |
MYSON
TECHNOLOGY
MTV212A32
(Rev. 1.2)
Revision 1.2 - 16 - 2000/07/04
and IICpass flag is set, the host may access the EEPROM directly. Software can test the HSCL condition by
reading the Hbusy flag, which is set in case of HSCL=0, and keeps high for 100uS after the HSCL's rising
edge. S/W can launch the master IIC transmit/receive by clearing the P bit. Once P=0, MTV212A32 will hold
HSCL low to isolate the host's access to EEPROM. A summary of master IIC access is illustrated as follows.
7.4.1. To write IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV212A32 transmit this byte, a MbufI interrupt will be triggered.
4. Program can write MBUF to transfer next byte or set P bit to stop.
* Please see the attachments about "Master IIC Transmit Timing".
7.4.2. To read IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV212A32 transmit this byte, a MbufI interrupt will be triggered.
4. Set or reset the MAckO flag according to the IIC protocol.
5. Read out MBUF the useless byte to continue the data transfer.
6. After the MTV212A32 receives a new byte, the MbufI interrupt is triggered again.
7. Read MBUF also trigger the next receive operation, but set P bit before read can terminate the operation.
* Please see the attachments about "Master IIC Receive Timing".
Reg name
IICCTR
IICSTUS
IICSTUS
INTFLG
INTFLG
INTEN
MBUF
RCABUF
TXABUF
SLVAADR
RCBBUF
TXBBUF
SLVBADR
DBUF
addr
00h (r/w)
01h (r)
02h (r)
03h (r)
03h (w)
04h (w)
05h (r/w)
06h (r)
06h (w)
07h (w)
08h (r)
08h (w)
09h (w)
0Ah (w)
bit7
DDC2
WadrB
MAckIn
TXBI
bit6
bit5
bit4
bit3
bit2
MAckO
bit1
P
bit0
S
WadrA
Hifreq
RCBI
SlvRWB
Hbusy
SlvBMI
SlvBMI
ESlvBMI
Master IIC receive/transmit data buffer
Slave A IIC receive buffer
Slave A IIC transmit buffer
Slave A IIC address
Slave B IIC receive buffer
Slave B IIC transmit buffer
Slave B IIC address
DDC1 transmit data buffer
SAckIn
SLVS
SlvAlsb1 SlvAlsb0
TXAI
RCAI
SlvAMI
SlvAMI
ESlvAMI
DbufI
MbufI
MbufI
EMbufI
ETXBI
ERCBI
ETXAI
ERCAI
EDbufI
ENSlvA
ENSlvB
IICCTR
(r/w) : IIC interface control register.
DDC2 = 1
= 0
MAckO = 1
= 0
S, P
=
↑
, 0
= X,
↑
= 1, X
= X, 0
* A write/read MBUF operation can be recognized only after 10us of the MbufI flag's rising edge.
→
MTV212A32 is in DDC2 mode, write "0" can clear it.
→
MTV212A32 is in DDC1 mode.
→
In master receive mode, NACK is returned by MTV212A32.
→
In master receive mode, ACK is returned by MTV212A32.
→
Start condition when Master IIC is not during transfer.
→
Stop condition when Master IIC is not during transfer.
→
Will resume transfer after a read/write MBUF operation.
→
Force HSCL low and occupy the master IIC bus.
IICSTUS
(r) :
IIC interface status register.
WadrB = 1
→
The data in RCBBUF is word address.
WadrA = 1
→
The data in RCABUF is word address.
SlvRWB = 1
→
Current transfer is slave transmit
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相關(guān)代理商/技術(shù)參數(shù) |
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