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參數(shù)資料
| 型號(hào)： | MTV018 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | IC TXRX PHY 10/100 3.3V 48LQFP |
| 中文描述： | 超級(jí)屏幕顯示器 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 139K |
| 代理商： | MTV018 |
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MTV018 Revision 4.0 10/21/1999
MTV018
MYSON
TECHNOLOGY
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format
(a), but not from format (c) back to format (a) and (b). The alternation between transmission formats is config-
ured as the state diagram shown in Figure 3 on page 5.
3.2 Address bus administrator
The administrator manages bus address arbitration of internal registers or user fonts RAM during external
data write in. The external data write through serial data interface to registers must be synchronized by inter-
nal display timing. In addition, the administrator also provides automatic increment to address bus when exter-
nal write using format (c).
3.3 Vertical display control
The vertical display control can generates different vertical display sizes for most display standards in current
monitors. The vertical display size is calculated with the information of double character height bit(CHS), verti-
TABLE 1.
The configuration of transmission formats.
Address
b7
b6
b5
b4
b3
b2
b1
b0
Format
Address Bytes
of Display Reg.
Row
1
0
0
0
0
x
x
R3
C3
R2
C2
R1
C1
R0
C0
a,b,c
a,b
Column
ab
Column
c
Row
Column
ab
Column
c
Row
Column
ab
Column
c
C4
0
1
x
C4
C3
C2
C1
C0
c
Attribute Bytes
of Display Reg.
1
0
0
0
1
x
x
R3
C3
R2
C2
R1
C1
R0
C0
a,b,c
a,b
C4
0
1
x
C4
C3
C2
C1
C0
c
User Fonts
RAM
1
0
1
0
x
x
x
R2
C2
R1
C1
R0
C0
a,b,c
a,b
C5
C4
C3
0
1
C5
C4
C3
C2
C1
C0
c
Initiate
ROW
COL
c
COL
ab
DA
c
DA
ab
1, X
0 1
0 0
X X
X X
0 1
1, X
1, X
format (a)
format (b)
format (c)
X, X
0, X
Input = b7, b6
0, 0
FIGURE 3. Transmission state diagram
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