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參數(shù)資料
| 型號： | MTV018 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | IC TXRX PHY 10/100 3.3V 48LQFP |
| 中文描述： | 超級屏幕顯示器 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 139K |
| 代理商： | MTV018 |
12/16
MTV018 Revision 4.0 10/21/1999
MTV018
MYSON
TECHNOLOGY
= (1, 0)
32MHz < Pixel rate < 64MHz
= (1, 1)
64MHz < Pixel rate < 96MHz
(vi)7.5K ohm:
= (0, 0)
8.5MHz < Pixel rate < 17MHz
= (0, 1)
17MHz < Pixel rate < 34MHz
= (1, 0)
34MHz < Pixel rate < 68MHz
= (1, 1)
68MHz < Pixel rate < 96MHz
(vii)under or equal to 6.2K ohm:
= (0, 0)
9.5MHz < Pixel rate < 19MHz
= (0, 1)
19MHz < Pixel rate < 38MHz
= (1, 0)
38MHz < Pixel rate < 76MHz
= (1, 1)
76MHz < Pixel rate < 96MHz
where Pixel rate = VCLK Freq = HFLB Freq * HORR * 12
The initial value is (0, 0) after power up.
Notes :
1. That is, if HORR is specified, and RP resister = 12K ohm, then (VCO1, VCO0)
= (0, 0) if 6000/(HORR * 12) < HFLB Freq (KHz) < 12000/(HORR * 12)
= (0, 1) if 12000/(HORR * 12) < HFLB Freq (KHZ) < 24000/(HORR * 12)
= (1, 0) if 24000/(HORR * 12) < HFLB Freq (KHZ) < 48000/(HORR * 12)
= (1, 1) if 48000/(HORR * 12) < HFLB Freq (KHZ) < 96000/(HORR * 12)
2. It is necessary to wait for the PLL to become stable while (i) the HORR register is changed; (ii) the (VCO1,
VCO0) bits is changed; (iii) the horizontal signal (HFLB) is changed.
3. When PLL is unstable, don't write data in any address except Column 15,17,18 of Row 15. If data is written
in any other address, a malfunction may occur.
3.11 PWM D/A converter
There are 8 open-drain PWM D/A outputs (PWM0 to PWM7). These PWM D/A converter outputs pulse width
are programmable by writing data to Column 19 to 26 registers of Row 15 with 8-bit resolution to control the
pulse width duration from 0/256 to 255/256. And the sampling rate is selected by (VCO1, VCO0) shown as
table 4. In applications, all open-drain output pins should be pulled-up by external resistors to supply voltage
(5V to 9V) for desired output range.
ROW 15
PWMDA0 - PWMDA7 - Define the output pulse width of pin PWM0 to PWM7.
TABLE 4. PWMCK Frequency and PWMDA sampling rate
(VCO1, VCO0)
( 0, 0 )
( 0, 1 )
( 1, 0 )
( 1 ,1 )
PWMCK Freq (6M ~ 12MHz)
HFLB Freq * HORR * 12
HFLB Freq * HORR * 6
HFLB Freq * HORR * 3
HFLB Freq * HORR * 3 / 2
PWMDA sampling rate (23K ~ 47KHz)
HFLB Freq * HORR * 12 / 256
HFLB Freq * HORR * 6 / 256
HFLB Freq * HORR * 3 / 256
HFLB Freq * HORR * 3 / 512
Column 19
|
Column 26
b7
b6
b5
b4
PWMDA0
|
PWMDA7
b3
b2
b1
b0
MSB
LSB
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