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MTV018 Revision 4.0 10/21/1999
MTV018
MYSON
TECHNOLOGY
Super On-Screen-Display
FEATURES
GENERAL DESCRIPTION
BLOCK DIAGRAM
Horizontal sync input may be up to 120 KHz.
On-chip PLL circuitry up to 96 MHz.
Programmable horizontal resolutions up to 1524 dots per dis-
play row.
942 bytes display registers to control full screen display.
Full screen display consists of 15 (rows) by 30 (columns) char-
acters.
12 x 18 dot matrix per character.
Total 256 characters and graphic fonts including 248 mask
ROM fonts and 8 programmable RAM fonts.
8 color selectable maximum per display character.
Double character height and/or width control.
Programmable positioning for display screen center.
Bordering, shadowing and blinking effect.
Programmable vertical character height (18 to 71 lines) control.
Row to row spacing register to manipulate the constant display
height.
4 programmable background windows with multi-level operation
Software clears for display frame.
Polarity selectable to Hsync and Vsync inputs.
Auto detection for input edge bounce distortion between Hsync
and Vsync inputs.
Half tone and fast blanking output.
Software force blank function for external display.
8 channels 8 bits PWM D/A converters output.
Provide a clock output synchronous to the incoming Hsync for
external PWM D/A.
Compatible to SPI bus or I
2
C interface.
I
2
C interface with address 7AH (Slave address is mask option).
16 pins, 20 pins or 24 pins PDIP package.
MTV018 is designed for monitor applications to dis-
play the built-in characters or fonts onto monitor
screen. The display operation is by transferring data
and control information from micro controller to RAM
through a serial data interface. It can execute full
screen display automatically and specific functions
such as character bordering, shadowing, blinking,
double height and width, font by font color control,
frame positioning, frame size control by character
height and horizontal display resolution, and window-
ing effect. Moreover, MTV018 also provide 8 PWM
DAC channels with 8 bits resolution and a PWM
clock output for external digital to analog control.
SERIAL DATA
INTERFACE
ADDRESS BUS
ADMINISTRATOR
VERTICAL
DISPLAY
CONTROL
DISPLAY & ROW
CONTROL
REGISTERS
COLOUR
ENCODER
WINDOWS &
FRAME
CONTROL
W
W
W
F
B
LUMAR
LUMAG
LUMAB
BLINK
VCLKX
DATA
VERTD
HORD
CH
8
8
7
BSEN
SHADOW
OSDENB
HSP
VSP
HORIZONTAL
DISPLAY CONTROL
PHASE LOCK LOOP
8
DATA
LPN
CWS
VCLKS
5
DATA
CWS
CHS
8
LUMAR
LUMAG
LUMAB
BLINK
CRADDR
8
LUMA
BORDER
ARWDB
HDREN
VCLKX
HORD8
CH
CHS
VERTD
7
8
LPN
NROW
VDREN
5
RCADDR
DADDR
FONTADDR
WINADDR
PWMADDR
5
9
9
5
5
ARWDB
HDREN
VDREN
NROW
DATA
ROW, COL
ACK
8
9
CHARACTER ROM
USER FONT RAM
LUMINANCE &
BORDGER
GENERATOR
VDD
VSS
VDDA
VSSA
ROUT
GOUT
BOUT
FBKG
HTONE
HFLB
RP
VCO
VFLB
SSB
SCK
SDA
VSP
HSP
PWM D/A
CONVERTER
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
8
DATA
8
POWER ON
RESET
PRB