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參數(shù)資料
| 型號(hào)： | MTV012E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded CRT Monitor Controller OTP Version |
| 中文描述： | CRT顯示器8051嵌入式控制器OTP版 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 104K |
| 代理商： | MTV012E |
MYSON
TECHNOLOGY
MTV012E
MTV012E Revision 1.2 12/23/1998
9/14
STF
= 1
= 0
Port 4 data output value.
→
Enables STOUT output.
→
Disables STOUT output.
P4OUT
(w) :
INTFLG
(w) :
Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding
interrupt enable bit is set, the 8051 core's INT1 source will be driven by a zero level.
Software MUST clear this register while serving the interrupt routine.
HPRchg= 1
→
No action.
= 0
→
Clears HSYNC presence change flag.
VPRchg= 1
→
No action.
= 0
→
Clears VSYNC presence change flag.
HPLchg= 1
→
No action.
= 0
→
Clears HSYNC polarity change flag.
VPLchg= 1
→
No action.
= 0
→
Clears VSYNC polarity change flag.
HFchg = 1
→
No action.
= 0
→
Clears HSYNC frequency change flag.
VFchg = 1
→
No action.
= 0
→
Clears VSYNC frequency change flag.
INTFLG
(r) :
Interrupt flag.
HPRchg= 1
VPRchg= 1
HPLchg= 1
VPLchg= 1
HFchg = 1
VFchg = 1
→
Indicates an HSYNC presence change.
→
Indicates a VSYNC presence change.
→
Indicates an HSYNC polarity change.
→
Indicates a VSYNC polarity change.
→
Indicates an HSYNC frequency change or counter overflow.
→
Indicates a VSYNC frequency change or counter overflow.
INTEN
(w) :
Interrupt enabler.
EHPR = 1
EVPR = 1
EHPL
= 1
EVPL
= 1
EHF
= 1
EVF
= 1
→
Enables HSYNC presence change interrupt.
→
Enables VSYNC presence change interrupt.
→
Enables HSYNC polarity change interrupt.
→
Enables VSYNC polarity change interrupt.
→
Enables HSYNC frequency change / counter overflow interrupt.
→
Enables VSYNC frequency change / counter overflow interrupt.
5. DDC & IIC Interface
5.1 DDC1 Mode
MTV012E enters DDC1 mode after Reset. In this mode, VSYNC is used as a data clock. The HSCL pin
should remain at high. The data output to the HSDA pin is taken from 8 bytes of FIFO in MTV012E.
MTV012E fetches the data byte from FIFO, then sends it in a 9-bit packet format which includes a null bit
(=1) as packet separator. The software program should load EDID data (original stored in EEPROM)
into FIFO and take care of the FIFO depth. FIFO sets the FIFOI (FIFO low interrupt) flag when there are
fewer than N (N=2,3,4 or 5 controlled by LS1, LS0) bytes to be output to the HSDA pin. To prevent FIFO
from emptying, software needs to write EDID data to FIFO as soon as FIFOI is set. On the other hand,
FIFO sets the FIFOH flag when its capacity is full. Software should not write additional data to FIFO in
such an instance. The FIFOI interrupt can be masked or enabled by an EFIFO control bit. A simple way
to control FIFO is to set (LS1, LS0=1,0) and enable FIFOI interrupt, then software may load 4 bytes into
FIFO each time a FIFOI interrupt arises. A special control bit "LDFIFO" can reduce the software effort
when EDID data is stored in EEPROM. If LDFIFO=1, FIFO will be automatically loaded with MBUF data
when software reads MBUF XFR.
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