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參數(shù)資料
| 型號(hào)： | MTV012E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded CRT Monitor Controller OTP Version |
| 中文描述： | CRT顯示器8051嵌入式控制器OTP版 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 104K |
| 代理商： | MTV012E |
MYSON
TECHNOLOGY
MTV012E
MTV012E Revision 1.2 12/23/1998
3/14
P2.1
P2.2
P2.3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
-
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
General purpose I/O
General purpose I/O
General purpose I/O
PWM DAC output / General purpose I/O
(open-drain)
PWM DAC output / General purpose I/O
(open-drain)
PWM DAC output / General purpose I/O
(open-drain)
PWM DAC output / General purpose I/O
(open-drain)
Self-test video output / General purpose output
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
PWM DAC output (open-drain)
Positive power supply
DA13/P2.4
DA12/P2.5
DA11/P2.6
DA10/P2.7
STOUT/P4.2
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
VDD
3.0 FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
MTV012E includes all the 8051 functions with the following exceptions:
1.1 PSEN, ALE, RD and WR pins are disabled. The external RAM access is restricted to XFRs within
MTV012E.
1.2 Port0, port3.3 and ports3.5 ~ 3.7 are not general purpose I/O ports. They are dedicated to monitoring
control/DAC pins.
1.3 INT1 and T1 input pins are not provided.
1.4 Ports2.4 ~ 2.7 are shared with DAC pins; ports3.0 ~ 3.2 and port3.4 are shared with monitor control
pins.
In addition, there are 2 timers, 5 interrupt sources and a serial interface compatible with the standard
8051. The Txd/Rxd (P3.0/P3.1) pins are shared with the DDC interface. INT0/T0 pins are shared with
the IIC interface. An extra option can be used to switch the INT0 source from P3.2 to P2.0. This feature
maintains an external interrupt source when the IIC interface is enabled.
Note: All registers listed in this document reside in the external RAM area (XFR). For the internal
RAM memory map, please refer to the 8051 spec.
reg name
PADMOD
addr
30h (w)
bit7
SINT0
bit6
X
bit5
DDCE
bit4
IICE
bit3
DA13E
bit2
DA12E
bit1
DA11E
bit0
DA10E
SINT0 = 1
→
INT0 source is pin #21.
→
INT0 source is pin #12.
→
Pin #10 is HSCL; pin #11 is HSDA.
→
Pin #10 is P3.0/Rxd; pin #11 is P3.1/Txd.
→
Pin #12 is ISDA; pin #14 is ISCL.
→
Pin #12 is P3.2/(INT0*); pin #14 is P3.4/T0.
→
Pin #25 is DA13.
→
Pin #25 is P2.4.
→
Pin #26 is DA12.
→
Pin #26 is P2.5.
= 0
DDCE = 1
= 0
= 1
= 0
IICE
DA13E = 1
= 0
DA12E = 1
= 0
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相關(guān)代理商/技術(shù)參數(shù) |
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| MTV018 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Super On-Screen-Display |
| MTV021 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced Super On-Screen Display |
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