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參數(shù)資料
| 型號(hào)： | MTV004 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | On-Screen Display Shrink Version |
| 中文描述： | 屏幕顯示收縮版本 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 88K |
| 代理商： | MTV004 |
MYSON
TECHNOLOGY
MTV004
MTV004 Revision 4.0 06/24/1999
5/9
The vertical display center for a full-screen display may be figured out according to the information of the
vertical starting position register (VERTD) and VFLB input. The vertical delay, starting from the falling edge of
VFLB, is calculated using the following equation:
Vertical delay time = (VERTD * 4 + 1) * H
H = 1 horizontal line display time
Table 2. Repeat Line Character Weight
CH5 - CH0
CH5,CH4=11
CH5,CH4=10
CH5,CH4=0x
CH3=1
CH2=1
CH1=1
CH0=1
Repeat Line Weight
(+16)*3
(+16)*2
+16
+8
+4
+2
+1
Table 3. Repeat Line Character Number
Repeat Line #
7
8
-
v
-
-
v
v
v
Repeat Line
Weight
+1
+2
+4
+8
+16
0
-
-
-
-
v
1
-
-
-
v
v
2
-
-
v
-
v
3
-
-
-
v
v
4
-
v
-
-
v
5
-
-
-
v
v
6
-
-
v
-
v
9
-
-
-
v
v
10
-
-
v
-
v
11
-
-
-
v
v
12
-
v
-
-
v
13
-
-
-
v
v
14
-
-
v
-
v
15
-
-
-
v
v
-
-
-
Note: " v " means the nth line in the character would be repeated once, while "-" means the nth line in the
character would not be repeated.
3.4 Horizontal Control Logic
The horizontal control logic is used to generate control timing for the horizontal display based on the double
character width bit (CWS), horizontal positioning register (HORD) and HFLB input. A horizontal display line
consists of 384 dots, which include 288 dots for 24 display characters and 96 dots for the remaining blank
region. The horizontal delay starting from the HFLB falling edge is calculated using the following equation:
horizontal delay time = (HORD * 6 + 61)* P - phase error detection pulse width
P= 1 pixel display time = 1 horizontal display time / 384
3.5 Phase Lock Loop (PLL)
On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB. The frequency of VCLK is
determined using the following equation:
VCLK = HFLB Freq.* 384 ,
The frequency ranges from 3.84MHz to 38.4MHz. See Table 4.
Table 4. Frequency Range
HFLB
VCLK
10KHz to 100KHz
3.84MHz to 38.4MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MTV012A | 8051 Embedded CRT Monitor Controller Mask Version |
| MTV012E | 8051 Embedded CRT Monitor Controller OTP Version |
| MTV018 | IC TXRX PHY 10/100 3.3V 48LQFP |
| MTV021 | Enhanced Super On-Screen Display |
| MTV021N20 | Enhanced Super On-Screen Display |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MTV012A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded CRT Monitor Controller Mask Version |
| MTV012E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8051 Embedded CRT Monitor Controller OTP Version |
| MTV016 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Enhanced On-Screen-Display Controller |
| MTV016N-10 | 制造商:Myson Century Inc 功能描述:IC, PDIP16 |
| MTV016N-18 | 制造商:Myson Century Inc 功能描述:IC, PDIP16 |
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