參數(shù)資料
型號(hào)： MTV003
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： Microprocessor Compatible Monitor Controller
中文描述： 微處理器兼容顯示器控制器
文件頁(yè)數(shù)： 7/13頁(yè)
文件大小： 224K
代理商： MTV003
MYSON
TECHNOLOGY
MTV003N
(MTV003)
MTV003 Revision 2.3 07/01/1998
7/13
= 0,1
= 1,0
-> force Vpol
-> force Vpol
= 1.
= 0.
Reg 2
(read)
: H-Freq low byte.
Reg 2
(write)
: Begins V-Freq count. To read the value in V-Freq registers, the write command (
Reg2)
must
be issued first.
Reg3
(read)
: V-Freq Count Finish flag, V-Freq high bit.
1. VCFF
= 1 -> valid,
2. VF8
= the high bit of V-Freq.
= 0 -> not valid.
Reg3
(write)
: Controls test and clock modes.
1. TEST
= 0
= 1
= 0
= 1
-> Normal mode.
->
Test mode, not allowed in applications.
-> CLK = X1 divided by 2 (for 8MHz crystal power-on [default]).
-> CLK = X1 (for 4MHz crystal power-on [default]).
2. CLK4M
Reg4
(read)
: V-Freq low byte.
Reg4
(write)
: Reserved.
Reg5
(write)
: Reserved.
Reg6
(write)
: Controls the delay of HBLANK output (7 bits).
(HBD7 - 0)
= 10000000
-> Directly bypasses Hsync to output.
= 01000000
-> Min. propagation delay (approximately 300ns).
= 00000000
-> T + 500ns.
= 00000001
-> 2T + 500ns.
= 00111111
-> 64T + 500ns.
Reg7
(write)
: Controls the width of HBLANK output (7 bits).
(HBW7 - 0)
= 10000000
-> Directly bypasses Hsync to output.
= 01000000
-> Min. width (approximately 300ns).
= 00000000
-> T + 500ns.
= 00000001
-> 2T + 500ns.
= 00111111
-> 64T + 500ns.
Reg8
(write)
: Reserved.
Reg9
(write)
: Controls the width of Vblank output (7 bits).
(VBW7 - 0)
= 1-000000
-> Directly bypasses Vsync to output.
= 0-000000
-> Min. width (approximately 8us).
= 0-000001
-> 16 + 8(us).
= 0-111111
-> 16 * 63 + 8(us) = 1.016ms.
Reg10
(write)
: Output pulse width control for DA0.
Reg11
(write)
: Output pulse width control for DA1.
Reg12
(write)
: Output pulse width control for DA2.
Reg13
(write)
: Reserved.
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