參數(shù)資料
型號(hào)： MTV003
廠商： Electronic Theatre Controls, Inc.
英文描述： Microprocessor Compatible Monitor Controller
中文描述： 微處理器兼容顯示器控制器
文件頁(yè)數(shù)： 6/13頁(yè)
文件大?。?/td> 224K
代理商： MTV003
MYSON
TECHNOLOGY
MTV003N
(MTV003)
MTV003 Revision 2.3 07/01/1998
6/13
Reg4
Reg5
Reg6
Reg7
Reg8
Reg9
Reg10
Reg11
Reg12
Reg13
Reg14
Reg15
Reg16
Reg17
Reg18
I
Reg25
Reg26
Reg27
Reg28
Reg29
Reg30
Reg31
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
I
11001
11010
11011
11100
11101
11110
11111
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Reserved
Reserved
HBD3
HBW3
Reserved
VBW3
DA0b3
DA1b3
DA2b3
Reserved
Reserved
Reserved
STbsh
x
HBD0
HBW0
HBD1
HBW1
HBD2
HBW2
HBD4
HBW4
HBD5
HBW5
HBD6
HBW6
HBD7
HBW7
VBW0
DA0b0
DA1b0
DA2b0
VBW1
DA0b1
DA1b1
DA2b1
VBW2
DA0b2
DA1b2
DA2b2
VBW4
DA0b4
DA1b4
DA2b4
VBW5
DA0b5
DA1b5
DA2b5
x
VBW7
DA0b7
DA1b7
DA2b7
DA0b6
DA1b6
DA2b6
STF
x
RT0
x
RT1
x
Selft
x
x
x
x
x
x
x
Reserved
1
1
1
1
1
1
XA0b0
XA1b0
XA2b0
XA3b0
XA4b0
XA0b1
XA1b1
XA2b1
XA3b1
XA4b1
XA0b2
XA1b2
XA2b2
XA3b2
XA4b2
XA0b3
XA1b3
XA2b3
XA3b3
XA4b3
XA0b4
XA1b4
XA2b4
XA3b4
XA4b4
XA0b5
XA1b5
XA2b5
XA3b5
XA4b5
XA0b6
XA1b6
XA2b6
XA3b6
XA4b5
XA0b7
XA1b7
XA2b7
XA3b7
XA4b7
Reserved
* The above x may represent any data.
- Command Descriptions
Reg0
(write)
: Begins the H-Freq count. To read the value in the H-Freq registers, the write command (
Reg0)
needs to be issued first.
Reg0
(read)
: The status of polarity, presence and static level for HS and VS.
1. Hpol, Vpol
2. HSpre, VSpre, HVpre
3. Hsl, Vsl
* HVpre represents the status of the composite (H/V) presence in HS. Hsl or Vsl is valid only
when HSpre or VSpre is not present.
= 1 -> positive,
= 1 -> present,
= 1 -> high,
= 0 -> negative.
= 0 -> not present.
= 0 -> low.
Reg1
(read)
: Hfreq Count Finish flags, Hfreq high bit.
1. HCFF
2. HF10 - HF8
= 1 -> valid,
= 3 high bit of Hfreq.
= 0 -> not valid.
Reg1
(write)
: Selects the source of VBLANK and controls the polarity status of Hpol, Vpol
and SYNC output polarity.
1. HVcvs
= 1 -> VBLANK is extracted from HS.
= 0 -> VBLANK is extracted from VS.
2. HBpl = 1 -> negative HBLANK output,
3. VBpl = 1 -> negative VBLANK output,
* After power-on, HBpl and VBpl shall be initialized to 0.
4. Hpf1, Hpf0
= 0,0 or 1,1
-> Hpol
= 0,1
-> force Hpol
= 1,0
-> force Hpol
5. Vpf1, Vpf0
= 0,0 or 1,1
-> Vpol
= 0 -> positive HBLANK output.
= 0 -> positive VBLANK output.
= x, by auto detection.
= 1.
= 0.
= x, by auto detection.
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