參數(shù)資料
型號(hào): MTD2955ET4
廠商: ON SEMICONDUCTOR
元件分類: JFETs
英文描述: 12 A, 60 V, 0.3 ohm, P-CHANNEL, Si, POWER, MOSFET
封裝: CASE 369A-13, DPAK-3
文件頁(yè)數(shù): 10/11頁(yè)
文件大?。?/td> 278K
代理商: MTD2955ET4
MTD2955E
http://onsemi.com
8
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
DPAK
5.80
0.228
2.58
0.101
1.6
0.063
6.20
0.244
3.0
0.118
6.172
0.243
mm
inches
SCALE 3:1
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a
surface mount device is determined by TJ(max), the
maximum rated junction temperature of the die, RqJA, the
thermal resistance from the device JunctiontoAmbient,
and the operating temperature, TA. Using the values
provided on the data sheet, PD can be calculated as follows:
PD =
TJ(max) TA
RqJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For a DPAK
device, PD is calculated as follows.
PD = 150°C 25°C
71.4°C/W
= 1.75 Watts
The 71.4°C/W for the DPAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 1.75 Watts. There are
other alternatives to achieving higher power dissipation
from the surface mount packages. One is to increase the area
of the drain pad. By increasing the area of the drain pad, the
power dissipation can be increased. Although one can
almost double the power dissipation with this method, one
will be giving up area on the printed circuit board which can
defeat the purpose of using surface mount technology. For
example, a graph of RqJA versus drain pad area is shown in
Figure 15.
Figure 15. Thermal Resistance versus Drain Pad
Area for the DPAK Package (Typical)
A, Area (square inches)
Board Material = 0.0625″
G10/FR4, 2 oz Copper
R
,
Thermal
Resistance,
Junction
to
Ambient
(C/W)
θ JA
°
80
100
60
40
20
10
8
6
4
2
0
3.0 Watts
5.0 Watts
TA = 25°C
1.75 Watts
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
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